📄 16bit counter.vhd
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-- VHDL X_16Bit_Counter
-- 2010 5 27 14 58 32
-- Created By "Altium Designer VHDL Generator"
-- "Copyright (c) 2002-2004 Altium Limited"
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-- VHDL X_16Bit_Counter
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Library IEEE;
Use IEEE.std_logic_1164.all;
Entity FPGA_16BitCounter Is
port
(
ADD0 : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=ADD0
ADD1 : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=ADD1
ADD2 : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=ADD2
ADD3 : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=ADD3
ADD4 : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=ADD4
ADD5 : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=ADD5
ADD6 : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=ADD6
ADD7 : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=ADD7
ADD8 : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=ADD8
ADD9 : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=ADD9
ADD10 : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=ADD10
ADD11 : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=ADD11
ADD12 : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=ADD12
ADD13 : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=ADD13
ADD14 : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=ADD14
ADD15 : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=ADD15
CLK : In STD_LOGIC; -- ObjectKind=Port|PrimaryId=CLK
CLR : In STD_LOGIC; -- ObjectKind=Port|PrimaryId=CLR
D : In STD_LOGIC_VECTOR(15 DOWNTO 0); -- ObjectKind=Port|PrimaryId=D[15..0]
EDN : In STD_LOGIC; -- ObjectKind=Port|PrimaryId=EDN
ENP : In STD_LOGIC; -- ObjectKind=Port|PrimaryId=ENP
ENT : In STD_LOGIC -- ObjectKind=Port|PrimaryId=ENT
);
attribute MacroCell : boolean;
attribute Part_name : string;
attribute Part_name of FPGA_16BitCounter : Entity is "EPM7128";
attribute PinNum : string;
attribute PinNum of ADD0 : Signal is "1";
attribute PinNum of ADD1 : Signal is "2";
attribute PinNum of ADD2 : Signal is "3";
attribute PinNum of ADD3 : Signal is "4";
attribute PinNum of ADD4 : Signal is "5";
attribute PinNum of ADD5 : Signal is "6";
attribute PinNum of ADD6 : Signal is "7";
attribute PinNum of ADD7 : Signal is "8";
attribute PinNum of ADD8 : Signal is "9";
attribute PinNum of ADD9 : Signal is "10";
attribute PinNum of ADD10 : Signal is "11";
attribute PinNum of ADD11 : Signal is "12";
attribute PinNum of ADD12 : Signal is "13";
attribute PinNum of ADD13 : Signal is "14";
attribute PinNum of ADD14 : Signal is "15";
attribute PinNum of ADD15 : Signal is "16";
attribute PinNum of CLK : Signal is "54";
attribute PinNum of CLR : Signal is "56";
attribute PinNum of D : Signal is "7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22";
attribute PinNum of EDN : Signal is "41";
attribute PinNum of ENP : Signal is "43";
attribute PinNum of ENT : Signal is "42";
End FPGA_16BitCounter;
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architecture structure of FPGA_16BitCounter is
Component A_74161 -- ObjectKind=Part|PrimaryId=U1|SecondaryId=1
port
(
A : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U1-A
B : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U1-B
C : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U1-C
CLK : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U1-CLK
CLRN : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U1-CLRN
D : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U1-D
ENP : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U1-ENP
ENT : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U1-ENT
LDN : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U1-LDN
QA : out STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U1-QA
QB : out STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U1-QB
QC : out STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U1-QC
QD : out STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U1-QD
RCO : out STD_LOGIC -- ObjectKind=Pin|PrimaryId=U1-RCO
);
End Component;
Signal NamedSignal_ENP : STD_LOGIC; -- ObjectKind=Net|PrimaryId=ENP
Signal NamedSignal_ENT : STD_LOGIC; -- ObjectKind=Net|PrimaryId=ENT
Signal NamedSignal_LON : STD_LOGIC; -- ObjectKind=Net|PrimaryId=LON
Signal PinSignal_U1_QA : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_QA
Signal PinSignal_U1_QB : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_QB
Signal PinSignal_U1_QC : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_QC
Signal PinSignal_U1_QD : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_QD
Signal PinSignal_U1_RCO : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_RCO
Signal PinSignal_U2_QA : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU2_QA
Signal PinSignal_U2_QB : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU2_QB
Signal PinSignal_U2_QC : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU2_QC
Signal PinSignal_U2_QD : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU2_QD
Signal PinSignal_U2_RCO : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU2_RCO
Signal PinSignal_U3_QA : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU3_QA
Signal PinSignal_U3_QB : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU3_QB
Signal PinSignal_U3_QC : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU3_QC
Signal PinSignal_U3_QD : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU3_QD
Signal PinSignal_U4_QA : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU4_QA
Signal PinSignal_U4_QB : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU4_QB
Signal PinSignal_U4_QC : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU4_QC
Signal PinSignal_U4_QD : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU4_QD
Signal PinSignal_U4_RCO : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_CLK
begin
U4 : A_74161 -- ObjectKind=Part|PrimaryId=U4|SecondaryId=1
Port Map
(
CLK => PinSignal_U2_RCO, -- ObjectKind=Pin|PrimaryId=U4-CLK
CLRN => CLR, -- ObjectKind=Pin|PrimaryId=U4-CLRN
ENP => NamedSignal_ENP, -- ObjectKind=Pin|PrimaryId=U4-ENP
ENT => NamedSignal_ENT, -- ObjectKind=Pin|PrimaryId=U4-ENT
LDN => NamedSignal_LON, -- ObjectKind=Pin|PrimaryId=U4-LDN
QA => PinSignal_U4_QA, -- ObjectKind=Pin|PrimaryId=U4-QA
QB => PinSignal_U4_QB, -- ObjectKind=Pin|PrimaryId=U4-QB
QC => PinSignal_U4_QC, -- ObjectKind=Pin|PrimaryId=U4-QC
QD => PinSignal_U4_QD, -- ObjectKind=Pin|PrimaryId=U4-QD
RCO => PinSignal_U4_RCO -- ObjectKind=Pin|PrimaryId=U4-RCO
);
U3 : A_74161 -- ObjectKind=Part|PrimaryId=U3|SecondaryId=1
Port Map
(
CLK => PinSignal_U1_RCO, -- ObjectKind=Pin|PrimaryId=U3-CLK
CLRN => CLR, -- ObjectKind=Pin|PrimaryId=U3-CLRN
ENP => ENP, -- ObjectKind=Pin|PrimaryId=U3-ENP
ENT => ENT, -- ObjectKind=Pin|PrimaryId=U3-ENT
LDN => EDN, -- ObjectKind=Pin|PrimaryId=U3-LDN
QA => PinSignal_U3_QA, -- ObjectKind=Pin|PrimaryId=U3-QA
QB => PinSignal_U3_QB, -- ObjectKind=Pin|PrimaryId=U3-QB
QC => PinSignal_U3_QC, -- ObjectKind=Pin|PrimaryId=U3-QC
QD => PinSignal_U3_QD -- ObjectKind=Pin|PrimaryId=U3-QD
);
U2 : A_74161 -- ObjectKind=Part|PrimaryId=U2|SecondaryId=1
Port Map
(
CLK => CLK, -- ObjectKind=Pin|PrimaryId=U2-CLK
CLRN => CLR, -- ObjectKind=Pin|PrimaryId=U2-CLRN
ENP => NamedSignal_ENP, -- ObjectKind=Pin|PrimaryId=U2-ENP
ENT => NamedSignal_ENT, -- ObjectKind=Pin|PrimaryId=U2-ENT
LDN => NamedSignal_LON, -- ObjectKind=Pin|PrimaryId=U2-LDN
QA => PinSignal_U2_QA, -- ObjectKind=Pin|PrimaryId=U2-QA
QB => PinSignal_U2_QB, -- ObjectKind=Pin|PrimaryId=U2-QB
QC => PinSignal_U2_QC, -- ObjectKind=Pin|PrimaryId=U2-QC
QD => PinSignal_U2_QD, -- ObjectKind=Pin|PrimaryId=U2-QD
RCO => PinSignal_U2_RCO -- ObjectKind=Pin|PrimaryId=U2-RCO
);
U1 : A_74161 -- ObjectKind=Part|PrimaryId=U1|SecondaryId=1
Port Map
(
CLK => PinSignal_U4_RCO, -- ObjectKind=Pin|PrimaryId=U1-CLK
CLRN => CLR, -- ObjectKind=Pin|PrimaryId=U1-CLRN
ENP => ENP, -- ObjectKind=Pin|PrimaryId=U1-ENP
ENT => ENT, -- ObjectKind=Pin|PrimaryId=U1-ENT
LDN => EDN, -- ObjectKind=Pin|PrimaryId=U1-LDN
QA => PinSignal_U1_QA, -- ObjectKind=Pin|PrimaryId=U1-QA
QB => PinSignal_U1_QB, -- ObjectKind=Pin|PrimaryId=U1-QB
QC => PinSignal_U1_QC, -- ObjectKind=Pin|PrimaryId=U1-QC
QD => PinSignal_U1_QD, -- ObjectKind=Pin|PrimaryId=U1-QD
RCO => PinSignal_U1_RCO -- ObjectKind=Pin|PrimaryId=U1-RCO
);
-- Signal Assignments
---------------------
ADD0 <= PinSignal_U2_QA; -- ObjectKind=Net|PrimaryId=NetU2_QA
ADD1 <= PinSignal_U2_QB; -- ObjectKind=Net|PrimaryId=NetU2_QB
ADD10 <= PinSignal_U1_QC; -- ObjectKind=Net|PrimaryId=NetU1_QC
ADD11 <= PinSignal_U1_QD; -- ObjectKind=Net|PrimaryId=NetU1_QD
ADD12 <= PinSignal_U3_QA; -- ObjectKind=Net|PrimaryId=NetU3_QA
ADD13 <= PinSignal_U3_QB; -- ObjectKind=Net|PrimaryId=NetU3_QB
ADD14 <= PinSignal_U3_QC; -- ObjectKind=Net|PrimaryId=NetU3_QC
ADD15 <= PinSignal_U3_QD; -- ObjectKind=Net|PrimaryId=NetU3_QD
ADD2 <= PinSignal_U2_QC; -- ObjectKind=Net|PrimaryId=NetU2_QC
ADD3 <= PinSignal_U2_QD; -- ObjectKind=Net|PrimaryId=NetU2_QD
ADD4 <= PinSignal_U4_QA; -- ObjectKind=Net|PrimaryId=NetU4_QA
ADD5 <= PinSignal_U4_QB; -- ObjectKind=Net|PrimaryId=NetU4_QB
ADD6 <= PinSignal_U4_QC; -- ObjectKind=Net|PrimaryId=NetU4_QC
ADD7 <= PinSignal_U4_QD; -- ObjectKind=Net|PrimaryId=NetU4_QD
ADD8 <= PinSignal_U1_QA; -- ObjectKind=Net|PrimaryId=NetU1_QA
ADD9 <= PinSignal_U1_QB; -- ObjectKind=Net|PrimaryId=NetU1_QB
NamedSignal_ENP <= ENP; -- ObjectKind=Net|PrimaryId=ENP
NamedSignal_ENT <= ENT; -- ObjectKind=Net|PrimaryId=ENT
NamedSignal_LON <= EDN; -- ObjectKind=Net|PrimaryId=LON
end structure;
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