arm926ejs_compile.tcl

arm 公司的design complier 综合脚本 对于初学synposys 公司的软件很有帮助

###################################################################################################################
# This confidential and proprietary software may be used only as
# authorised by a licensing agreement from ARM Limited
#
#   (c) COPYRIGHT 2002-2003 ARM Limited
#   (c) COPYRIGHT 2002-2003 Synopsys Inc.
#       ALL RIGHTS RESERVED
#
# The entire notice above must be reproduced on all authorised
# copies and copies may only be made to the extent permitted
# by a licensing agreement from ARM Limited.
#
###################################################################################################################
#
# File Name           : arm926ejs_compile.tcl
# RCS Revision	      : 1.6
# Release Information : ARM926EJS_r0p5-00rel0
#
# Purpose 	      : Compile script for the ARM926EJS
#		  
# Tool Version        : 2003.03-1
#
#
###################################################################################################################
sh date
sh hostname
set rm_task     synthesis

# -----------------------------------------------------------------------------------------------------------------
# Source the configuration script
# -----------------------------------------------------------------------------------------------------------------
set_svf ./synthesis/data/ARM926EJS-compile.svf
source -echo -verbose ./scripts/arm926ejs_config.tcl

#------------------------------------------------------------------------------------------------------------------
# Analyze the RTL.
#------------------------------------------------------------------------------------------------------------------

define_design_lib work -path ./synthesis/work

if { $rm_use_presto } {
  set hdlin_enable_presto true
} else {
  set hdlin_enable_presto false
}

set hdlin_check_no_latch true
set hdlin_enable_vpp true

if { $rm_vhdl_rtl } {
  source -echo -verbose ./scripts/arm926ejs_vhdl.tcl
  analyze -f vhdl $rtl_image
} else {
  source -echo -verbose ./scripts/arm926ejs_verilog.tcl
  analyze -f verilog $rtl_image
}

# -----------------------------------------------------------------------------------------------------------------
# Define the clock gating style.
# -----------------------------------------------------------------------------------------------------------------

if { $rm_clock_gating } {
  remove_license Power-Optimization
  set dc_shell_status [ get_license Power-Optimization ]
  while {  $dc_shell_status == 0 } {
      redirect /dev/null { set dc_shell_status [get_license Power-Optimization] }
  }
}


if { $rm_clock_gating } {
	set hdlin_no_group_register true
	if { $rm_icg_name != ""} {
  	set_clock_gating_style 	-sequential_cell latch  -positive_edge_logic $rm_icg_name -control_point before  \
  				-control_signal scan_enable -max_fanout 32
  } else {  				
  	set_clock_gating_style 	-sequential_cell latch -control_point before  \
  				-control_signal scan_enable -max_fanout 8
  }
}

# -----------------------------------------------------------------------------------------------------------------
# Elaborate, uniquify, link and check the Design
# -----------------------------------------------------------------------------------------------------------------

if { $rm_vhdl_rtl } {
  if { $rm_clock_gating } {
  	elaborate -architecture "synth" -gate_clock ARM926EJS
  } else {
  	elaborate -architecture "synth" ARM926EJS
  }
} else {
  if { $rm_clock_gating } {
  	elaborate -architecture verilog -gate_clock ARM926EJS
  } else {
  	elaborate -architecture verilog ARM926EJS
  }
}

current_design ARM926EJS
uniquify
link

if { $rm_clock_gating } {
	propagate_constraints -gate_clock -output ./synthesis/reports/ARM926EJS.propagate_constraints
}

check_design >  ./synthesis/reports/ARM926EJS.check

#------------------------------------------------------------------------------------------------------------------
# Create test ports on the design.
# -----------------------------------------------------------------------------------------------------------------

remove_license Test-Compiler
set dc_shell_status [ get_license Test-Compiler ]
while {  $dc_shell_status == 0 } {
    redirect /dev/null { set dc_shell_status [get_license Test-Compiler] }
}

rm_create_test_ports

#------------------------------------------------------------------------------------------------------------------
# Setup a test-ready compile
# -----------------------------------------------------------------------------------------------------------------

set test_scan_enable_port_naming_style SCANENABLE%s
set_scan_signal test_scan_enable -port SCANENABLE
set test_scan_in_port_naming_style ${rm_scan_in}%s
set test_scan_out_port_naming_style ${rm_scan_out}%s

set_scan_configuration -methodology full_scan -style multiplexed_flip_flop 

set_test_hold 1 TESTMODE
set_logic_zero [ get_ports INTEST ]
set_logic_zero [ get_ports EXTEST ]

if { $rm_clock_gating } {
	hookup_testports
}

# -----------------------------------------------------------------------------------------------------------------
# Define port lists.
# -----------------------------------------------------------------------------------------------------------------

set clock_ports         [get_ports {CLK} ]
set scan_ports         	[list SCANENABLE ${rm_scan_in}* ${rm_scan_out}*]
set inputs              [remove_from_collection [all_inputs] $clock_ports];
set outputs             [all_outputs]

# -----------------------------------------------------------------------------------------------------------------
# Constrain the design.
# -----------------------------------------------------------------------------------------------------------------

create_clock -name CLK -period $rm_clock_period [ get_ports {CLK} ]
	set_clock_uncertainty $rm_clock_uncertainty [ get_clocks {CLK} ]
	set_clock_transition 0 [ get_clocks {CLK} ]
	set_clock_latency $rm_clock_latency [ get_clocks {CLK} ]

create_clock -name VCLK -period $rm_clock_period 
	set_clock_uncertainty $rm_clock_uncertainty [ get_clocks {VCLK} ]
	set_clock_latency -min [expr $rm_clock_latency - $rm_clock_uncertainty] [get_clocks {VCLK} ]
	set_clock_latency -max $rm_clock_latency [get_clocks {VCLK} ]

if { $rm_clock_gating } {
	set latches [all_registers -clock CLK -level -clock_pins]
	set cg_latches [filter_collection $latches "full_name =~ */clk_gate_*/latch/*"]
	set_clock_latency $rm_icg_latency $cg_latches
}

source -echo -verbose ./scripts/arm926ejs_constraints.tcl

set_max_transition $rm_max_transition ARM926EJS
set_max_area 0

# -----------------------------------------------------------------------------------------------------------------
# Define the design environment.
# -----------------------------------------------------------------------------------------------------------------

set_ideal_net [list HRESETn DBGnTRST DBGTCKEN SCANENABLE ]

set_driving_cell -cell $rm_driving_cell -pin $rm_driving_pin $inputs
set_load [expr [load_of $rm_loading_pin ] * 4 ] $outputs

set auto_wire_load_selection true
set_wire_load_mode segmented

set_operating_conditions $rm_operating_condition

# -----------------------------------------------------------------------------------------------------------------
# Setup the compile options
# -----------------------------------------------------------------------------------------------------------------

if { $rm_compile_ultra } {
  set dc_shell_status [ set_ultra_optimization true -force ]
  while {  $dc_shell_status == 0 } {
      redirect /dev/null { set dc_shell_status [ set_ultra_optimization true -force ] }
  }
}

if { $rm_clock_gating } {
  remove_license Power-Optimization
  set dc_shell_status [ get_license Power-Optimization ]
  while {  $dc_shell_status == 0 } {
      redirect /dev/null { set dc_shell_status [get_license Power-Optimization] }
  }
}

remove_license Test-Compiler
set dc_shell_status [ get_license Test-Compiler ]
while {  $dc_shell_status == 0 } {
    redirect /dev/null { set dc_shell_status [get_license Test-Compiler] }
}

set hlo_disable_datapath_optimization true
set dw_prefer_mc_inside true
set_resource_implementation use_fastest
set_fix_multiple_port_nets -feedthroughs -outputs -constants
set_critical_range [expr $rm_critical_range * $rm_clock_period] ARM926EJS

if { $rm_ungroup } {
        set_dont_touch [find design a9ejsMulDP ] true
        ungroup -all -flatten
        set_dont_touch [find design a9ejsMulDP ] false
}

set_ungroup dummy_buffer*

write -hierarchy -f db -o ./synthesis/data/ARM926EJS-gtech.db

# -----------------------------------------------------------------------------------------------------------------
# Free up the HDL-Compiler license                           
# -----------------------------------------------------------------------------------------------------------------

if { $rm_vhdl_rtl } {
  remove_license VHDL-Compiler
} else {
  remove_license HDL-Compiler
}


# -----------------------------------------------------------------------------------------------------------------
# Compile the design. Use RPP, DC compile , DC compile_ultra or PC compile_physical.
# -----------------------------------------------------------------------------------------------------------------

if { $rm_use_rpp } {
	set_floorplan_options -utilization $rm_rpp_util -aspect_ratio $rm_rpp_ratio
	compile_physical -timing_driven_congestion -area_recovery -scan -mpc
} else {
	if { $rm_rtl2pg } {
		read_pdef -allow_physical_ports ./floorplan/data/ARM926EJS.pdef
		compile_physical  -map_effort high -timing_driven_congestion -area_recovery -scan
	} else {
                if { $rm_compile_ultra } {
                        compile_ultra -scan
                } else {
                        compile -map_effort high -area_effort medium -scan
                }
	}
}

# -----------------------------------------------------------------------------------------------------------------
# Free up the licenses.
# -----------------------------------------------------------------------------------------------------------------

if { $rm_compile_ultra } {
  set_ultra_optimization false
}

if { $rm_clock_gating } {
  remove_license Power-Optimization
}

remove_license Test-Compiler

# -----------------------------------------------------------------------------------------------------------------
# Save the compiled design. Generate reports and quit.
# -----------------------------------------------------------------------------------------------------------------

set verilogout_higher_designs_first true
set verilogout_no_tri true

write -f db -hierarchy -o ./synthesis/data/ARM926EJS-compile.db
write -f verilog -hierarchy -o ./synthesis/data/ARM926EJS-compile.v
rm_write_sdc ./synthesis/data/ARM926EJS-compile.sdc

report_clock -attributes -skew > ./synthesis/reports/ARM926EJS-compile.clocks
report_hierarchy > ./synthesis/reports/ARM926EJS-compile.hier
report_compile_options > ./synthesis/reports/ARM926EJS-compile.options
report_resources -hierarchy > ./synthesis/reports/ARM926EJS-compile.resources

report_timing -max 32 -nets -nos > ./synthesis/reports/ARM926EJS-compile.timing
report_constraint -all_violators > ./synthesis/reports/ARM926EJS-compile.constraints
report_timing -loops > ./synthesis/reports/ARM926EJS-compile.loops
report_port -verbose > ./synthesis/reports/ARM926EJS-compile.port
all_registers -level_sensitive > ./synthesis/reports/ARM926EJS.latches

# ----------- Area reports --------------------------------

set rep_design_name [list ARM926EJS ARM926EJSCore ARM9EJS \
                          a926ejsBIU a926ejsMMU \
                          a926ejsDExt a926ejsIExt \
                          a926ICache a926DCache ]

set area_file  {./synthesis/reports/ARM926EJS-compile.area}
redirect $area_file { echo {} }

foreach design_name $rep_design_name {
      current_design $design_name
      redirect -append $area_file { echo {} }
      redirect -append $area_file { report_area }   
      redirect -append $area_file { echo {} }
}

redirect -append $area_file { echo {} }
redirect -append $area_file { echo {--- End of File ---} }


sh date
quit