sha1_top.vhd

sha_1加密运算模块

 
 
   OR_Q(31 downto 0) <= ( A_LOGA_Q(31 downto 0)) or ( A_LOGB_Q(31 downto 0));
 
 
   XOR_Q(31 downto 0) <= ( A_LOGA_Q(31 downto 0)) xor ( A_LOGB_Q(31 downto 0));
 
 
  A_LOGA_Q(31 downto 0) <= (visual_C4_O);
   process (RA1 , RA2 , RA3 , RA4 , A_LOGA_CTRL)
   begin
     case A_LOGA_CTRL(1 downto 0) is
       when "00" =>
         visual_C4_O <=  RA1(31 downto 0);
       when "01" =>
         visual_C4_O <=  RA2(31 downto 0);
       when "10" =>
         visual_C4_O <=  RA3(31 downto 0);
       when others =>
         visual_C4_O <=  RA4(31 downto 0);
     end case;
   end process;
 
 
  A_LOGB_Q(31 downto 0) <= (visual_C15_O);
   process (RB1 , RB2 , RB3 , RB4 , A_LOGB_CTRL)
   begin
     case A_LOGB_CTRL(1 downto 0) is
       when "00" =>
         visual_C15_O <=  RB1(31 downto 0);
       when "01" =>
         visual_C15_O <=  RB2(31 downto 0);
       when "10" =>
         visual_C15_O <=  RB3(31 downto 0);
       when others =>
         visual_C15_O <=  RB4(31 downto 0);
     end case;
   end process;
 
 
  CIRCLE1(31 downto 1) <= A_LOGA_Q(30 downto 0);
  CIRCLE1(0) <= A_LOGA_Q(31);
 
  CIRCLE5(31 downto 5) <= S86(26 downto 0);
  CIRCLE5(4 downto 0) <= S87(4 downto 0);
 
  CIRCLE30(31 downto 30) <= S88(1 downto 0);
  CIRCLE30(29 downto 0) <= S89(29 downto 0);
 
  NOT_Q(31 downto 0) <= not (A_LOGA_Q(31 downto 0));
 
  REGIN_Q(31 downto 0) <= (visual_C18_O);
   process (ADD_Q , AND_Q , OR_Q , XOR_Q , NOT_QQ , CIRCLE5 , CIRCLE30 , CIRCLE1 , REGIN_CTRL)
   begin
     case REGIN_CTRL(2 downto 0) is
       when "000" =>
         visual_C18_O <=  ADD_Q(31 downto 0);
       when "001" =>
         visual_C18_O <=  AND_Q(31 downto 0);
       when "010" =>
         visual_C18_O <=  OR_Q(31 downto 0);
       when "011" =>
         visual_C18_O <=  XOR_Q(31 downto 0);
       when "100" =>
         visual_C18_O <=  NOT_QQ(31 downto 0);
       when "101" =>
         visual_C18_O <=  CIRCLE5(31 downto 0);
       when "110" =>
         visual_C18_O <=  CIRCLE30(31 downto 0);
       when others =>
         visual_C18_O <=  CIRCLE1(31 downto 0);
     end case;
   end process;
 
 
  OUT_Q(127 downto 96) <= REG1QQ(31 downto 0);
  OUT_Q(95 downto 64) <= REG2QQ(31 downto 0);
  OUT_Q(63 downto 32) <= REG3QQ(31 downto 0);
  OUT_Q(31 downto 0) <= REG4QQ(31 downto 0);
 
  S86(26 downto 0) <= A_LOGA_Q(26 downto 0);
  S87(4 downto 0) <= A_LOGA_Q(31 downto 27);
 
  S88(1 downto 0) <= A_LOGA_Q(1 downto 0);
  S89(29 downto 0) <= A_LOGA_Q(31 downto 2);
 
  RA1(31 downto 0) <= RAM1_4QQ(127 downto 96);
  RA2(31 downto 0) <= RAM1_4QQ(95 downto 64);
  RA3(31 downto 0) <= RAM1_4QQ(63 downto 32);
  RA4(31 downto 0) <= RAM1_4QQ(31 downto 0);
 
  RB1(31 downto 0) <= RAM1QQ(127 downto 96);
  RB2(31 downto 0) <= RAM1QQ(95 downto 64);
  RB3(31 downto 0) <= RAM1QQ(63 downto 32);
  RB4(31 downto 0) <= RAM1QQ(31 downto 0);
 
  REG1QQ(31 downto 0) <= (visual_C20_Q);
 
 
  process (CLK , RST)
  begin
   if (RST = '0') then
      visual_C20_Q <= (others => '0');
   elsif (CLK'event and CLK = '1') then
 
      if (E1 = '1') then
        visual_C20_Q <= (REGIN_Q(31 downto 0));
      end if;
 
  end if;
  end process;
 
 
  REG2QQ(31 downto 0) <= (visual_C21_Q);
 
 
  process (CLK , RST)
  begin
   if (RST = '0') then
      visual_C21_Q <= (others => '0');
   elsif (CLK'event and CLK = '1') then
 
      if (E2 = '1') then
        visual_C21_Q <= (REGIN_Q(31 downto 0));
      end if;
 
  end if;
  end process;
 
 
  REG3QQ(31 downto 0) <= (visual_C22_Q);
 
 
  process (CLK , RST)
  begin
   if (RST = '0') then
      visual_C22_Q <= (others => '0');
   elsif (CLK'event and CLK = '1') then
 
      if (E3 = '1') then
        visual_C22_Q <= (REGIN_Q(31 downto 0));
      end if;
 
  end if;
  end process;
 
 
  REG4QQ(31 downto 0) <= (visual_C23_Q);
 
 
  process (CLK , RST)
  begin
   if (RST = '0') then
      visual_C23_Q <= (others => '0');
   elsif (CLK'event and CLK = '1') then
 
      if (E4 = '1') then
        visual_C23_Q <= (REGIN_Q(31 downto 0));
      end if;
 
  end if;
  end process;
 
 
  NOT_QQ(31 downto 0) <= (visual_C25_O);
   process (A_LOGA_Q , NOT_Q , NOT_CTRL)
   begin
     case NOT_CTRL is
       when '0' =>
         visual_C25_O <=  A_LOGA_Q(31 downto 0);
       when others =>
         visual_C25_O <=  NOT_Q(31 downto 0);
     end case;
   end process;
 
end SHA1_TIXI;
----------------------------------------------------
--  
--  Library Name :  SHA1_LEAST
--  Unit    Name :  SHA1_ARC
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_UNSIGNED.all;
entity SHA1_ARC is
  port (
        BUSY : out std_logic;
        CLK : in std_logic;
        E : in std_logic;
        OV : out std_logic;
        RAM1_4QQ : in std_logic_vector(127 downto 0 );
        RAM1_4S : out std_logic_vector(1 downto 0 );
        RAMQQ1 : in std_logic_vector(127 downto 0 );
        RST : in std_logic;
        SADDR1 : out std_logic_vector(2 downto 0 );
        SADDR2 : out std_logic_vector(2 downto 0 );
        SADDR4 : out std_logic_vector(2 downto 0 );
        SCEN1 : out std_logic;
        SCEN2 : out std_logic;
        SCEN4 : out std_logic;
        SHA1_OUT : out std_logic_vector(127 downto 0 );
        SWEN1 : out std_logic;
        SWEN2 : out std_logic;
        SWEN4 : out std_logic
        );
 
 
end SHA1_ARC;
 
 
use work.all;
architecture SHA1_ARC of SHA1_ARC is
 
  signal A_LOGA_CTRL : std_logic_vector(1 downto 0 );
  signal A_LOGB_CTRL : std_logic_vector(1 downto 0 );
  signal E1 : std_logic;
  signal E2 : std_logic;
  signal E3 : std_logic;
  signal E4 : std_logic;
  signal NOT_CTRL : std_logic;
  signal REGIN_CTRL : std_logic_vector(2 downto 0 );
  component SHA1_TIXI
      port (
            A_LOGA_CTRL : in std_logic_vector(1 downto 0 );
            A_LOGB_CTRL : in std_logic_vector(1 downto 0 );
            CLK : in std_logic;
            E1 : in std_logic;
            E2 : in std_logic;
            E3 : in std_logic;
            E4 : in std_logic;
            NOT_CTRL : in std_logic;
            OUT_Q : out std_logic_vector(127 downto 0 );
            RAM1_4QQ : in std_logic_vector(127 downto 0 );
            RAM1QQ : in std_logic_vector(127 downto 0 );
            REGIN_CTRL : in std_logic_vector(2 downto 0 );
            RST : in std_logic
            );
  end component;
  component SHA1_CTRL
      port (
            SCEN1 : out std_logic;
            SCEN2 : out std_logic;
            SCEN4 : out std_logic;
            SWEN1 : out std_logic;
            SWEN2 : out std_logic;
            SWEN4 : out std_logic;
            SADDR1 : out std_logic_vector(2 downto 0 );
            SADDR2 : out std_logic_vector(2 downto 0 );
            SADDR4 : out std_logic_vector(2 downto 0 );
            RAM1_4S : out std_logic_vector(1 downto 0 );
            A_LOGA_CTRL : out std_logic_vector(1 downto 0 );
            A_LOGB_CTRL : out std_logic_vector(1 downto 0 );
            NOT_CTRL : out std_logic;
            REGIN_CTRL : out std_logic_vector(2 downto 0 );
            CLK : in std_logic;
            RST : in std_logic;
            E1 : out std_logic;
            E2 : out std_logic;
            E3 : out std_logic;
            E4 : out std_logic;
            BUSY : out std_logic;
            E : in std_logic;
            OV : out std_logic
            );
  end component;
 
  -- Start Configuration Specification
  -- ++ for all : SHA1_TIXI use entity work.SHA1_TIXI(SHA1_TIXI);
  -- ++ for all : SHA1_CTRL use entity work.SHA1_CTRL(SHA1_CTRL);
  -- End Configuration Specification
 
begin
 
  C0: SHA1_TIXI
    port map (
              A_LOGA_CTRL => A_LOGA_CTRL(1 downto 0),
              A_LOGB_CTRL => A_LOGB_CTRL(1 downto 0),
              CLK => CLK,
              E1 => E1,
              E2 => E2,
              E3 => E3,
              E4 => E4,
              NOT_CTRL => NOT_CTRL,
              OUT_Q => SHA1_OUT(127 downto 0),
              RAM1_4QQ => RAM1_4QQ(127 downto 0),
              RAM1QQ => RAMQQ1(127 downto 0),
              REGIN_CTRL => REGIN_CTRL(2 downto 0),
              RST => RST
              );
 
  C1: SHA1_CTRL
    port map (
              SCEN1 => SCEN1,
              SCEN2 => SCEN2,
              SCEN4 => SCEN4,
              SWEN1 => SWEN1,
              SWEN2 => SWEN2,
              SWEN4 => SWEN4,
              SADDR1 => SADDR1(2 downto 0),
              SADDR2 => SADDR2(2 downto 0),
              SADDR4 => SADDR4(2 downto 0),
              RAM1_4S => RAM1_4S(1 downto 0),
              A_LOGA_CTRL => A_LOGA_CTRL(1 downto 0),
              A_LOGB_CTRL => A_LOGB_CTRL(1 downto 0),
              NOT_CTRL => NOT_CTRL,
              REGIN_CTRL => REGIN_CTRL(2 downto 0),
              CLK => CLK,
              RST => RST,
              E1 => E1,
              E2 => E2,
              E3 => E3,
              E4 => E4,
              BUSY => BUSY,
              E => E,
              OV => OV
              );
end SHA1_ARC;
----------------------------------------------------
--  
--  Library Name :  SHA1_LEAST
--  Unit    Name :  SHA1_TUP
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_UNSIGNED.all;
entity SHA1_TUP is
  port (
        BUSY : out std_logic;
        CLK : in std_logic;
        E_SHA1 : in std_logic;
        OV : out std_logic;
        RAM1_4QQ : in std_logic_vector(127 downto 0 );
        RAM1_4S : out std_logic_vector(1 downto 0 );
        RAMQQ1 : in std_logic_vector(127 downto 0 );
        RST : in std_logic;
        SADDR1 : out std_logic_vector(2 downto 0 );
        SADDR2 : out std_logic_vector(2 downto 0 );
        SADDR4 : out std_logic_vector(2 downto 0 );
        SCEN1 : out std_logic;
        SCEN2 : out std_logic;
        SCEN4 : out std_logic;
        SHA1_OUT : out std_logic_vector(127 downto 0 );
        SWEN1 : out std_logic;
        SWEN2 : out std_logic;
        SWEN4 : out std_logic
        );
 
 
end SHA1_TUP;
 
 
use work.all;
architecture SHA1_TUP of SHA1_TUP is
 
  component SHA1_ARC
      port (
            BUSY : out std_logic;
            CLK : in std_logic;
            E : in std_logic;
            OV : out std_logic;
            RAM1_4QQ : in std_logic_vector(127 downto 0 );
            RAM1_4S : out std_logic_vector(1 downto 0 );
            RAMQQ1 : in std_logic_vector(127 downto 0 );
            RST : in std_logic;
            SADDR1 : out std_logic_vector(2 downto 0 );
            SADDR2 : out std_logic_vector(2 downto 0 );
            SADDR4 : out std_logic_vector(2 downto 0 );
            SCEN1 : out std_logic;
            SCEN2 : out std_logic;
            SCEN4 : out std_logic;
            SHA1_OUT : out std_logic_vector(127 downto 0 );
            SWEN1 : out std_logic;
            SWEN2 : out std_logic;
            SWEN4 : out std_logic
            );
  end component;
 
  -- Start Configuration Specification
  -- ++ for all : SHA1_ARC use entity work.SHA1_ARC(SHA1_ARC);
  -- End Configuration Specification
 
begin
 
  C0: SHA1_ARC
    port map (
              BUSY => BUSY,
              CLK => CLK,
              E => E_SHA1,
              OV => OV,
              RAM1_4QQ => RAM1_4QQ(127 downto 0),
              RAM1_4S => RAM1_4S(1 downto 0),
              RAMQQ1 => RAMQQ1(127 downto 0),
              RST => RST,
              SADDR1 => SADDR1(2 downto 0),
              SADDR2 => SADDR2(2 downto 0),
              SADDR4 => SADDR4(2 downto 0),
              SCEN1 => SCEN1,
              SCEN2 => SCEN2,
              SCEN4 => SCEN4,
              SHA1_OUT => SHA1_OUT(127 downto 0),
              SWEN1 => SWEN1,
              SWEN2 => SWEN2,
              SWEN4 => SWEN4
              );
end SHA1_TUP;