rijndael_de_top.vhd

AES解密运算模块

Q <= "10011001";
when "11101111" =>
Q <= "01100001";
when "11110000" =>
Q <= "00010111";
when "11110001" =>
Q <= "00101011";
when "11110010" =>
Q <= "00000100";
when "11110011" =>
Q <= "01111110";
when "11110100" =>
Q <= "10111010";
when "11110101" =>
Q <= "01110111";
when "11110110" =>
Q <= "11010110";
when "11110111" =>
Q <= "00100110";
when "11111000" =>
Q <= "11100001";
when "11111001" =>
Q <= "01101001";
when "11111010" =>
Q <= "00010100";
when "11111011" =>
Q <= "01100011";
when "11111100" =>
Q <= "01010101";
when "11111101" =>
Q <= "00100001";
when "11111110" =>
Q <= "00001100";
when "11111111" =>
Q <= "01111101";
when others =>null;
end case;
end process;
end;

----------------------------------------------------
--  
--  Library Name :  rijndael_min_new
--  Unit    Name :  DE_Ctrl
--  Unit    Type :  State Machine
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.STD_LOGIC_MISC.all;
entity DE_Ctrl is
  port (
        CLK : in std_logic;
        RST : in std_logic;
        E_PT : in std_logic;
        KEY_TYPE : in std_logic_vector(1 downto 0 );
        CIR_MUX : out std_logic_vector(3 downto 0 );
        DATA_MUX : out std_logic;
        KEY_MUX : out std_logic_vector(3 downto 0 );
        DE_KEY_E : out std_logic;
        CRYPT_END : out std_logic;
        E_CIR : out std_logic;
        XOR_CY_S : out std_logic;
        CT_BA_E : out std_logic;
        MIX_END : in std_logic;
        CRYPT_BUSY : out std_logic
        );
 
end DE_Ctrl;
 
 
architecture DE_Ctrl of DE_Ctrl is
 
  signal COUNT_ED : std_logic_vector(3 downto 0 );
  signal COUNT_MIX : std_logic_vector(6 downto 0 );
  signal CIR_COUNT : std_logic_vector(3 downto 0 );
 
  type visual_S18_states is (S18, S10, S11, S12, S13, S14, S5);
  signal visual_S18_current : visual_S18_states;
 
 
begin
 
 
 
  -- Synchronous process
  DE_Ctrl_S18:
  process (CLK, RST)
  begin
 
    if (RST = '0') then
      COUNT_MIX<="0000000";
      COUNT_ED<="0000";
      CIR_COUNT<="0000";
      CRYPT_END<='0';
      DATA_MUX<='0';
      E_CIR<='0';
      DE_KEY_E<='0';
      XOR_CY_S<='0';
      CT_BA_E<='0';
      CRYPT_BUSY<='0';
      visual_S18_current <= S18;
    elsif (CLK'event and CLK = '1') then
 
      case visual_S18_current is
        when S18 =>
          if (E_PT = '1') then
            CRYPT_BUSY<='1';
            CIR_COUNT<="0000";
            E_CIR<='1';
            CT_BA_E<='0';
            visual_S18_current <= S10;
          else
            visual_S18_current <= S18;
          end if;
 
        when S10 =>
          if (CIR_COUNT = "1111") then
            E_CIR<='0';
            DE_KEY_E<='1';
            visual_S18_current <= S14;
          else
            CIR_COUNT<=CIR_COUNT+1;
            visual_S18_current <= S10;
          end if;
 
        when S11 =>
          if (MIX_END = '1') then
            CT_BA_E<='1';
            DATA_MUX<='1';
            COUNT_ED<=COUNT_ED+1;
            visual_S18_current <= S12;
          else
            COUNT_MIX<=COUNT_MIX+1;
            visual_S18_current <= S11;
          end if;
 
        when S12 =>
          if (KEY_TYPE = "00" and COUNT_ED = "1001") then
            E_CIR<='1';
            CIR_COUNT<="0000";
            CT_BA_E<='0';
            COUNT_ED<=COUNT_ED+1;
            visual_S18_current <= S13;
          elsif (KEY_TYPE = "01" and COUNT_ED = "1011") then
            E_CIR<='1';
            CIR_COUNT<="0000";
            CT_BA_E<='0';
            COUNT_ED<=COUNT_ED+1;
            visual_S18_current <= S13;
          elsif (KEY_TYPE = "10" and COUNT_ED = "1101") then
            E_CIR<='1';
            CIR_COUNT<="0000";
            CT_BA_E<='0';
            COUNT_ED<=COUNT_ED+1;
            visual_S18_current <= S13;
          else
            CIR_COUNT<="0000";
            E_CIR<='1';
            CT_BA_E<='0';
            visual_S18_current <= S10;
          end if;
 
        when S13 =>
          if (CIR_COUNT = "1111") then
            XOR_CY_S<='1';
            CRYPT_END<='1';
            DE_KEY_E<='0';
            visual_S18_current <= S5;
          else
            CIR_COUNT<=CIR_COUNT+1;
            visual_S18_current <= S13;
          end if;
 
        when S14 =>
          COUNT_MIX<="0000000";
          DE_KEY_E<='0';
          visual_S18_current <= S11;
 
        when S5 =>
          COUNT_MIX<="0000000";
          COUNT_ED<="0000";
          CIR_COUNT<="0000";
          CRYPT_END<='0';
          DATA_MUX<='0';
          E_CIR<='0';
          DE_KEY_E<='0';
          XOR_CY_S<='0';
          CT_BA_E<='0';
          CRYPT_BUSY<='0';
          visual_S18_current <= S18;
 
        when others =>
 
          COUNT_MIX<="0000000";
          COUNT_ED<="0000";
          CIR_COUNT<="0000";
          CRYPT_END<='0';
          DATA_MUX<='0';
          E_CIR<='0';
          DE_KEY_E<='0';
          XOR_CY_S<='0';
          CT_BA_E<='0';
          CRYPT_BUSY<='0';
          visual_S18_current <= S18;
      end case;
    end if;
  end process;
 
 
  KEY_MUX<=COUNT_ED;
  CIR_MUX<=CIR_COUNT;
end DE_Ctrl;
----------------------------------------------------
--  
--  Library Name :  rijndael_min_new
--  Unit    Name :  CRYPT_DE
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use ieee.STD_LOGIC_UNSIGNED.all;
entity CRYPT_DE is
  port (
        CLK : in std_logic;
        CRYPT_BUSY : out std_logic;
        CRYPT_END : out std_logic;
        CT : out std_logic_vector(127 downto 0 );
        E_PT : in std_logic;
        KEY_TYPE : in std_logic_vector(1 downto 0 );
        PT : in std_logic_vector(127 downto 0 );
        RST : in std_logic;
        SUBKEY0 : in std_logic_vector(127 downto 0 );
        SUBKEY1 : in std_logic_vector(127 downto 0 );
        SUBKEY10 : in std_logic_vector(127 downto 0 );
        SUBKEY11 : in std_logic_vector(127 downto 0 );
        SUBKEY12 : in std_logic_vector(127 downto 0 );
        SUBKEY13 : in std_logic_vector(127 downto 0 );
        SUBKEY14 : in std_logic_vector(127 downto 0 );
        SUBKEY2 : in std_logic_vector(127 downto 0 );
        SUBKEY3 : in std_logic_vector(127 downto 0 );
        SUBKEY4 : in std_logic_vector(127 downto 0 );
        SUBKEY5 : in std_logic_vector(127 downto 0 );
        SUBKEY6 : in std_logic_vector(127 downto 0 );
        SUBKEY7 : in std_logic_vector(127 downto 0 );
        SUBKEY8 : in std_logic_vector(127 downto 0 );
        SUBKEY9 : in std_logic_vector(127 downto 0 )
        );
 
 
end CRYPT_DE;
 
 
use work.all;
architecture CRYPT_DE of CRYPT_DE is
 
  signal BYTE_REPLACE : std_logic_vector(7 downto 0 );
  signal CIR_MUX : std_logic_vector(3 downto 0 );
  signal CRYPT_END_A : std_logic;
  signal CT_BA_E : std_logic;
  signal CT_BA_LOCK : std_logic_vector(127 downto 0 );
  signal CT_BACK : std_logic_vector(127 downto 0 );
  signal D_MID1 : std_logic_vector(127 downto 0 );
  signal D_MID2_SUBDE : std_logic_vector(7 downto 0 );
  signal DATA_MUX : std_logic;
  signal DE_KEY_E : std_logic;
  signal E_CIR : std_logic;
  signal KEY_MUX : std_logic_vector(3 downto 0 );
  signal MID_2 : std_logic_vector(127 downto 0 );
  signal MID_PT : std_logic_vector(127 downto 0 );
  signal MIX_END : std_logic;
  signal MIXCOLUMN_Q : std_logic_vector(127 downto 0 );
  signal OO_127 : std_logic_vector(127 downto 0 );
  signal SB_GROUP : std_logic_vector(127 downto 0 );
  signal SB_LOCK_E1 : std_logic;
  signal SB_LOCK_E10 : std_logic;
  signal SB_LOCK_E11 : std_logic;
  signal SB_LOCK_E12 : std_logic;
  signal SB_LOCK_E13 : std_logic;
  signal SB_LOCK_E14 : std_logic;
  signal SB_LOCK_E15 : std_logic;
  signal SB_LOCK_E16 : std_logic;
  signal SB_LOCK_E2 : std_logic;
  signal SB_LOCK_E3 : std_logic;
  signal SB_LOCK_E4 : std_logic;
  signal SB_LOCK_E5 : std_logic;
  signal SB_LOCK_E6 : std_logic;
  signal SB_LOCK_E7 : std_logic;
  signal SB_LOCK_E8 : std_logic;
  signal SB_LOCK_E9 : std_logic;
  signal SBOX_SB1 : std_logic_vector(7 downto 0 );
  signal SBOX_SB10 : std_logic_vector(7 downto 0 );
  signal SBOX_SB11 : std_logic_vector(7 downto 0 );
  signal SBOX_SB12 : std_logic_vector(7 downto 0 );
  signal SBOX_SB13 : std_logic_vector(7 downto 0 );
  signal SBOX_SB14 : std_logic_vector(7 downto 0 );
  signal SBOX_SB15 : std_logic_vector(7 downto 0 );
  signal SBOX_SB16 : std_logic_vector(7 downto 0 );
  signal SBOX_SB2 : std_logic_vector(7 downto 0 );
  signal SBOX_SB3 : std_logic_vector(7 downto 0 );
  signal SBOX_SB4 : std_logic_vector(7 downto 0 );
  signal SBOX_SB5 : std_logic_vector(7 downto 0 );
  signal SBOX_SB6 : std_logic_vector(7 downto 0 );
  signal SBOX_SB7 : std_logic_vector(7 downto 0 );
  signal SBOX_SB8 : std_logic_vector(7 downto 0 );
  signal SBOX_SB9 : std_logic_vector(7 downto 0 );
  signal SUBKEY : std_logic_vector(127 downto 0 );
  signal XOR_CY_S : std_logic;
  signal XOR_SCYCLE_IN : std_logic_vector(127 downto 0 );
  component SBOX8_8L_rijndael_5
      port (
            Q : out std_logic_vector(7 downto 0 );
            D : in std_logic_vector(7 downto 0 )
            );
  end component;
  component SUBKEY_DE_128
      port (
            CLK : in std_logic;
            MIX_END : out std_logic;
            DE_KEY_E : in std_logic;
            KEY_DE : out std_logic_vector(127 downto 0 );
            KEY_EN : in std_logic_vector(127 downto 0 );
            RST : in std_logic
            );
  end component;
  component DE_Ctrl
      port (
            CLK : in std_logic;
            RST : in std_logic;
            E_PT : in std_logic;
            KEY_TYPE : in std_logic_vector(1 downto 0 );
            CIR_MUX : out std_logic_vector(3 downto 0 );
            DATA_MUX : out std_logic;
            KEY_MUX : out std_logic_vector(3 downto 0 );
            DE_KEY_E : out std_logic;
            CRYPT_END : out std_logic;
            E_CIR : out std_logic;
            XOR_CY_S : out std_logic;
            CT_BA_E : out std_logic;
            MIX_END : in std_logic;
            CRYPT_BUSY : out std_logic
            );
  end component;
  signal visual_C78_Q : std_logic_vector(128 - 1 downto 0 );
  signal visual_C27_O : std_logic_vector(128 - 1 downto 0 );
  signal visual_C29_O : std_logic_vector(16 - 1 downto 0 );
  signal visual_C3_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C7_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C10_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C11_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C12_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C14_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C15_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C16_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C2_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C4_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C5_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C6_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C20_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C21_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C22_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C23_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C1_O : std_logic_vector(128 - 1 downto 0 );
  signal visual_C81_O : std_logic_vector(128 - 1 downto 0 );
  signal visual_C91_Q : std_logic_vector(128 - 1 downto 0 );
  signal visual_C30_Q : std_logic_vector(128 - 1 downto 0 );
  signal visual_C35_O : std_logic_vector(8 - 1 downto 0 );
 
  -- Start Configuration Specification
  -- ++ for all : SBOX8_8L_rijndael_5 use entity work.SBOX8_8L_rijndael_5(
  -- ++   Behavior);
  -- ++ for all : SUBKEY_DE_128 use entity work.SUBKEY_DE_128(SUBKEY_DE_128);
  -- ++ for all : DE_Ctrl use entity work.DE_Ctrl(DE_Ctrl);
  -- End Configuration Specification
 
begin
  CRYPT_END <= CRYPT_END_A;
 
  C9: SBOX8_8L_rijndael_5
    port map (
              Q => BYTE_REPLACE(7 downto 0),
              D => D_MID2_SUBDE(7 downto 0)
              );
 
  C33: SUBKEY_DE_128
    port map (
              CLK => CLK,
              MIX_END => MIX_END,
              DE_KEY_E => DE_KEY_E,
              KEY_DE => MIXCOLUMN_Q(127 downto 0),
              KEY_EN => SB_GROUP(127 downto 0),
              RST => RST
              );
 
  C31: DE_Ctrl
    port map (
              CLK => CLK,
              RST => RST,
              E_PT => E_PT,
              KEY_TYPE => KEY_TYPE(1 downto 0),
              CIR_MUX => CIR_MUX(3 downto 0),
              DATA_MUX => DATA_MUX,
              KEY_MUX => KEY_MUX(3 downto 0),
              DE_KEY_E => DE_KEY_E,
              CRYPT_END => CRYPT_END_A,
              E_CIR => E_CIR,
              XOR_CY_S => XOR_CY_S,
              CT_BA_E => CT_BA_E,
              MIX_END => MIX_END,
              CRYPT_BUSY => CRYPT_BUSY
              );
 
  SUBKEY(127 downto 0) <= (visual_C1_O);
   process (OO_127 , SUBKEY1 , SUBKEY2 , SUBKEY3 , SUBKEY4 , SUBKEY5 , SUBKEY6 , SUBKEY7 , SUBKEY8
             , SUBKEY9 , SUBKEY10 , SUBKEY11 , SUBKEY12 , SUBKEY13 , SUBKEY14 , KEY_MUX)
   begin
     case KEY_MUX(3 downto 0) is
       when "0000" =>
         visual_C1_O <=  OO_127(127 downto 0);
       when "0001" =>
         visual_C1_O <=  SUBKEY1(127 downto 0);
       when "0010" =>
         visual_C1_O <=  SUBKEY2(127 downto 0);
       when "0011" =>
         visual_C1_O <=  SUBKEY3(127 downto 0);
       when "0100" =>
         visual_C1_O <=  SUBKEY4(127 downto 0);
       when "0101" =>
         visual_C1_O <=  SUBKEY5(127 downto 0);
       when "0110" =>
         visual_C1_O <=  SUBKEY6(127 downto 0);
       when "0111" =>
         visual_C1_O <=  SUBKEY7(127 downto 0);
       when "1000" =>
         visual_C1_O <=  SUBKEY8(127 downto 0);
       when "1001" =>
         visual_C1_O <=  SUBKEY9(127 downto 0);
       when "1010" =>
         visual_C1_O <=  SUBKEY10(127 downto 0);
       when "1011" =>
         visual_C1_O <=  SUBKEY11(127 downto 0);
       when "1100" =>
         visual_C1_O <=  SUBKEY12(127 downto 0);
       when "1101" =>
         visual_C1_O <=  SUBKEY13(127 downto 0);
       when "1110" =>
         visual_C1_O <=  SUBKEY14(127 downto 0);
       when others =>
         visual_C1_O <=  OO_127(127 downto 0);
     end case;
   end process;
 
 
      OO_127(127 downto 0) <= (others => '0');
 
  MID_2(127 downto 0) <= (visual_C81_O);
   process (D_MID1 , CT_BA_LOCK , DATA_MUX)
   begin
     case DATA_MUX is
       when '0' =>
         visual_C81_O <=  D_MID1(127 downto 0);
       when others =>
         visual_C81_O <=  CT_BA_LOCK(127 downto 0);
     end case;
   end process;
 
 
   D_MID1(127 downto 0) <= ( SUBKEY0(127 downto 0)) xor ( MID_PT(127 downto 0));
 
 
  MID_PT(127 downto 0) <= (visual_C91_Q);
 
 
  process (CLK , RST)
  begin
   if (RST = '0') then
      visual_C91_Q <= (others => '0');
   elsif (CLK'event and CLK = '1') then
        visual_C91_Q <= (PT(127 downto 0));
 
 
  end if;
  end process;
 
 
  CT_BA_LOCK(127 downto 0) <= (visual_C30_Q);
 
 
  process (CLK , RST)
  begin
   if (RST = '0') then
      visual_C30_Q <= (others => '0');
   elsif (CLK'event and CLK = '1') then
 
      if (CT_BA_E = '1') then
        visual_C30_Q <= (CT_BACK(127 downto 0));
      end if;
 
  end if;
  end process;
 
 
  D_MID2_SUBDE(7 downto 0) <= (visual_C35_O);
   process (MID_2 , CIR_MUX)
   begin
     case CIR_MUX(3 downto 0) is
       when "0000" =>
         visual_C35_O <=  MID_2(127 downto 120);
       when "0001" =>
         visual_C35_O <=  MID_2(23 downto 16);
       when "0010" =>
         visual_C35_O <=  MID_2(47 downto 40);
       when "0011" =>
         visual_C35_O <=  MID_2(71 downto 64);
       when "0100" =>
         visual_C35_O <=  MID_2(95 downto 88);
       when "0101" =>
         visual_C35_O <=  MID_2(119 downto 112);
       when "0110" =>
         visual_C35_O <=  MID_2(15 dow