rijndael_de_top.vhd

AES解密运算模块

        DE_KEY_E32 : in std_logic;
        KEY_EN : in std_logic_vector(31 downto 0 );
        RST : in std_logic
        );
 
 
end MIXCOLUMN_DE;
 
 
use work.all;
architecture MIXCOLUMN_DE of MIXCOLUMN_DE is
 
  signal DA_CO_S : std_logic_vector(1 downto 0 );
  signal DE_IN_E : std_logic;
  signal DK32_E : std_logic;
  signal E_DK1 : std_logic;
  signal E_DK2 : std_logic;
  signal E_DK3 : std_logic;
  signal E_DK4 : std_logic;
  signal E_MP1 : std_logic;
  signal E_MP2 : std_logic;
  signal E_MP3 : std_logic;
  signal E_MP4 : std_logic;
  signal SECT_CON : std_logic_vector(1 downto 0 );
  component KEY_DE_GEN
      port (
            CLK : in std_logic;
            DA_CO_S : in std_logic_vector(1 downto 0 );
            DE_IN_E : in std_logic;
            DE_KEY : out std_logic_vector(31 downto 0 );
            DK32_E : in std_logic;
            E_DK1 : in std_logic;
            E_DK2 : in std_logic;
            E_DK3 : in std_logic;
            E_DK4 : in std_logic;
            E_MP1 : in std_logic;
            E_MP2 : in std_logic;
            E_MP3 : in std_logic;
            E_MP4 : in std_logic;
            KEY_EN : in std_logic_vector(31 downto 0 );
            RST : in std_logic;
            SECT_CON : in std_logic_vector(1 downto 0 )
            );
  end component;
  component DK_GEN_CTRL
      port (
            DA_CO_S : out std_logic_vector(1 downto 0 );
            SECT_CON : out std_logic_vector(1 downto 0 );
            E_MP1 : out std_logic;
            E_MP2 : out std_logic;
            E_MP3 : out std_logic;
            E_MP4 : out std_logic;
            E_DK1 : out std_logic;
            E_DK2 : out std_logic;
            E_DK3 : out std_logic;
            E_DK4 : out std_logic;
            CLK : in std_logic;
            RST : in std_logic;
            DE_KEY_E : in std_logic;
            DK32_E : out std_logic;
            DE_IN_E : out std_logic
            );
  end component;
 
  -- Start Configuration Specification
  -- ++ for all : KEY_DE_GEN use entity work.KEY_DE_GEN(KEY_DE_GEN);
  -- ++ for all : DK_GEN_CTRL use entity work.DK_GEN_CTRL(DK_GEN_CTRL);
  -- End Configuration Specification
 
begin
 
  C4: KEY_DE_GEN
    port map (
              CLK => CLK,
              DA_CO_S => DA_CO_S(1 downto 0),
              DE_IN_E => DE_IN_E,
              DE_KEY => DE_KEY(31 downto 0),
              DK32_E => DK32_E,
              E_DK1 => E_DK1,
              E_DK2 => E_DK2,
              E_DK3 => E_DK3,
              E_DK4 => E_DK4,
              E_MP1 => E_MP1,
              E_MP2 => E_MP2,
              E_MP3 => E_MP3,
              E_MP4 => E_MP4,
              KEY_EN => KEY_EN(31 downto 0),
              RST => RST,
              SECT_CON => SECT_CON(1 downto 0)
              );
 
  C8: DK_GEN_CTRL
    port map (
              DA_CO_S => DA_CO_S(1 downto 0),
              SECT_CON => SECT_CON(1 downto 0),
              E_MP1 => E_MP1,
              E_MP2 => E_MP2,
              E_MP3 => E_MP3,
              E_MP4 => E_MP4,
              E_DK1 => E_DK1,
              E_DK2 => E_DK2,
              E_DK3 => E_DK3,
              E_DK4 => E_DK4,
              CLK => CLK,
              RST => RST,
              DE_KEY_E => DE_KEY_E32,
              DK32_E => DK32_E,
              DE_IN_E => DE_IN_E
              );
end MIXCOLUMN_DE;
----------------------------------------------------
--  
--  Library Name :  rijndael_min_new
--  Unit    Name :  DE_128_CTRL
--  Unit    Type :  State Machine
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use ieee.STD_LOGIC_UNSIGNED.all;
entity DE_128_CTRL is
  port (
        DE_KEY_E : in std_logic;
        CLK : in std_logic;
        RST : in std_logic;
        DE_1 : out std_logic;
        DE_2 : out std_logic;
        DE_3 : out std_logic;
        DE_4 : out std_logic;
        DE128_S : out std_logic_vector(1 downto 0 );
        E_128 : out std_logic;
        E_DE_32 : out std_logic
        );
 
end DE_128_CTRL;
 
 
architecture DE_128_CTRL of DE_128_CTRL is
 
  signal DE_COUNT : std_logic_vector(4 downto 0 );
 
  type visual_S0_states is (S0, S14, S15, S16, S30, S39, S4, S40, S6, S8);
  signal visual_S0_current : visual_S0_states;
 
 
begin
 
 
 
  -- Synchronous process
  DE_128_CTRL_S0:
  process (CLK, RST)
  begin
 
    if (RST = '0') then
      DE_COUNT<="00000";
      DE128_S<="00";
      DE_1<='0';
      DE_2<='0';
      DE_3<='0';
      DE_4<='0';
      E_128<='0';
      E_DE_32<='0';
      visual_S0_current <= S0;
    elsif (CLK'event and CLK = '1') then
 
      case visual_S0_current is
        when S0 =>
          if (DE_KEY_E = '1') then
            E_128<='1';
            DE_1<='0';
            DE_2<='0';
            DE_3<='0';
            DE_4<='0';
            visual_S0_current <= S40;
          else
            visual_S0_current <= S0;
          end if;
 
        when S14 =>
          E_DE_32<='1';
          DE_COUNT<="00000";
          DE128_S<="01";
          DE_1<='0';
          DE_2<='0';
          DE_3<='0';
          DE_4<='0';
          visual_S0_current <= S4;
 
        when S15 =>
          E_DE_32<='1';
          DE_COUNT<="00000";
          DE128_S<="10";
          DE_1<='0';
          DE_2<='0';
          DE_3<='0';
          DE_4<='0';
          visual_S0_current <= S6;
 
        when S16 =>
          E_DE_32<='1';
          DE_COUNT<="00000";
          DE128_S<="11";
          DE_1<='0';
          DE_2<='0';
          DE_3<='0';
          DE_4<='0';
          visual_S0_current <= S8;
 
        when S30 =>
          if (DE_COUNT = "10011") then
            DE_1<='1';
            DE_2<='0';
            DE_3<='0';
            DE_4<='0';
            E_DE_32<='0';
            visual_S0_current <= S14;
          else
            DE_COUNT<=DE_COUNT+1;
            visual_S0_current <= S30;
          end if;
 
        when S39 =>
          if (DE_KEY_E = '1') then
            E_128<='1';
            DE_1<='0';
            DE_2<='0';
            DE_3<='0';
            DE_4<='0';
            visual_S0_current <= S40;
          else
            DE_COUNT<="00000";
            DE128_S<="00";
            DE_1<='0';
            DE_2<='0';
            DE_3<='0';
            DE_4<='0';
            E_128<='0';
            E_DE_32<='0';
            visual_S0_current <= S0;
          end if;
 
        when S4 =>
          if (DE_COUNT = "10011") then
            DE_1<='0';
            DE_2<='1';
            DE_3<='0';
            DE_4<='0';
            E_DE_32<='0';
            visual_S0_current <= S15;
          else
            DE_COUNT<=DE_COUNT+1;
            visual_S0_current <= S4;
          end if;
 
        when S40 =>
          E_DE_32<='1';
          DE_COUNT<="00000";
          DE128_S<="00";
          DE_1<='0';
          DE_2<='0';
          DE_3<='0';
          DE_4<='0';
          E_128<='0';
          visual_S0_current <= S30;
 
        when S6 =>
          if (DE_COUNT = "10011") then
            DE_1<='0';
            DE_2<='0';
            DE_3<='1';
            DE_4<='0';
            E_DE_32<='0';
            visual_S0_current <= S16;
          else
            DE_COUNT<=DE_COUNT+1;
            visual_S0_current <= S6;
          end if;
 
        when S8 =>
          if (DE_COUNT = "10011") then
            DE_1<='0';
            DE_2<='0';
            DE_3<='0';
            DE_4<='1';
            E_DE_32<='0';
            visual_S0_current <= S39;
          else
            DE_COUNT<=DE_COUNT+1;
            visual_S0_current <= S8;
          end if;
 
        when others =>
 
          DE_COUNT<="00000";
          DE128_S<="00";
          DE_1<='0';
          DE_2<='0';
          DE_3<='0';
          DE_4<='0';
          E_128<='0';
          E_DE_32<='0';
          visual_S0_current <= S0;
      end case;
    end if;
  end process;
 
end DE_128_CTRL;
----------------------------------------------------
--  
--  Library Name :  rijndael_min_new
--  Unit    Name :  SUBKEY_DE_128
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use ieee.STD_LOGIC_UNSIGNED.all;
entity SUBKEY_DE_128 is
  port (
        CLK : in std_logic;
        MIX_END : out std_logic;
        DE_KEY_E : in std_logic;
        KEY_DE : out std_logic_vector(127 downto 0 );
        KEY_EN : in std_logic_vector(127 downto 0 );
        RST : in std_logic
        );
 
 
end SUBKEY_DE_128;
 
 
use work.all;
architecture SUBKEY_DE_128 of SUBKEY_DE_128 is
 
  signal DE128_S : std_logic_vector(1 downto 0 );
  signal DE_1 : std_logic;
  signal DE_2 : std_logic;
  signal DE_3 : std_logic;
  signal DE_4 : std_logic;
  signal DE_KEY : std_logic_vector(31 downto 0 );
  signal DE_KEY1 : std_logic_vector(31 downto 0 );
  signal DE_KEY2 : std_logic_vector(31 downto 0 );
  signal DE_KEY3 : std_logic_vector(31 downto 0 );
  signal DE_KEY4 : std_logic_vector(31 downto 0 );
  signal E_128 : std_logic;
  signal E_DE_E32 : std_logic;
  signal KEY_EN_1 : std_logic_vector(31 downto 0 );
  signal KEY_EN_128 : std_logic_vector(127 downto 0 );
  signal KEY_EN_2 : std_logic_vector(31 downto 0 );
  signal KEY_EN_3 : std_logic_vector(31 downto 0 );
  signal KEY_EN_4 : std_logic_vector(31 downto 0 );
  signal KEY_EN_S : std_logic_vector(31 downto 0 );
  component DE_128_CTRL
      port (
            DE_KEY_E : in std_logic;
            CLK : in std_logic;
            RST : in std_logic;
            DE_1 : out std_logic;
            DE_2 : out std_logic;
            DE_3 : out std_logic;
            DE_4 : out std_logic;
            DE128_S : out std_logic_vector(1 downto 0 );
            E_128 : out std_logic;
            E_DE_32 : out std_logic
            );
  end component;
  component MIXCOLUMN_DE
      port (
            CLK : in std_logic;
            DE_KEY : out std_logic_vector(31 downto 0 );
            DE_KEY_E32 : in std_logic;
            KEY_EN : in std_logic_vector(31 downto 0 );
            RST : in std_logic
            );
  end component;
  signal visual_C1_Q : std_logic_vector(32 - 1 downto 0 );
  signal visual_C2_Q : std_logic_vector(32 - 1 downto 0 );
  signal visual_C3_Q : std_logic_vector(32 - 1 downto 0 );
  signal visual_C4_Q : std_logic_vector(32 - 1 downto 0 );
  signal visual_C12_O : std_logic_vector(32 - 1 downto 0 );
  signal visual_C8_Q : std_logic_vector(128 - 1 downto 0 );
 
  -- Start Configuration Specification
  -- ++ for all : DE_128_CTRL use entity work.DE_128_CTRL(DE_128_CTRL);
  -- ++ for all : MIXCOLUMN_DE use entity work.MIXCOLUMN_DE(MIXCOLUMN_DE);
  -- End Configuration Specification
 
begin
  MIX_END <= DE_4;
 
  C6: DE_128_CTRL
    port map (
              DE_KEY_E => DE_KEY_E,
              CLK => CLK,
              RST => RST,
              DE_1 => DE_1,
              DE_2 => DE_2,
              DE_3 => DE_3,
              DE_4 => DE_4,
              DE128_S => DE128_S(1 downto 0),
              E_128 => E_128,
              E_DE_32 => E_DE_E32
              );
 
  C9: MIXCOLUMN_DE
    port map (
              CLK => CLK,
              DE_KEY => DE_KEY(31 downto 0),
              DE_KEY_E32 => E_DE_E32,
              KEY_EN => KEY_EN_S(31 downto 0),
              RST => RST
              );
 
  DE_KEY1(31 downto 0) <= (visual_C1_Q);
 
 
  process (CLK , RST)
  begin
   if (RST = '0') then
      visual_C1_Q <= (others => '0');
   elsif (CLK'event and CLK = '1') then
 
      if (DE_1 = '1') then
        visual_C1_Q <= (DE_KEY(31 downto 0));
      end if;
 
  end if;
  end process;
 
 
  DE_KEY2(31 downto 0) <= (visual_C2_Q);
 
 
  process (CLK , RST)
  begin
   if (RST = '0') then
      visual_C2_Q <= (others => '0');
   elsif (CLK'event and CLK = '1') then
 
      if (DE_2 = '1') then
        visual_C2_Q <= (DE_KEY(31 downto 0));
      end if;
 
  end if;
  end process;
 
 
  DE_KEY3(31 downto 0) <= (visual_C3_Q);
 
 
  process (CLK , RST)
  begin
   if (RST = '0') then
      visual_C3_Q <= (others => '0');
   elsif (CLK'event and CLK = '1') then
 
      if (DE_3 = '1') then
        visual_C3_Q <= (DE_KEY(31 downto 0));
      end if;
 
  end if;
  end process;
 
 
  DE_KEY4(31 downto 0) <= (visual_C4_Q);
 
 
  process (CLK , RST)
  begin
   if (RST = '0') then
      visual_C4_Q <= (others => '0');
   elsif (CLK'event and CLK = '1') then
 
      if (DE_4 = '1') then
        visual_C4_Q <= (DE_KEY(31 downto 0));
      end if;
 
  end if;
  end process;
 
 
  KEY_EN_1(31 downto 0) <= KEY_EN_128(127 downto 96);
  KEY_EN_2(31 downto 0) <= KEY_EN_128(95 downto 64);
  KEY_EN_3(31 downto 0) <= KEY_EN_128(63 downto 32);
  KEY_EN_4(31 downto 0) <= KEY_EN_128(31 downto 0);
 
  KEY_EN_S(31 downto 0) <= (visual_C12_O);
   process (KEY_EN_1 , KEY_EN_2 , KEY_EN_3 , KEY_EN_4 , DE128_S)
   begin
     case DE128_S(1 downto 0) is
       when "00" =>
         visual_C12_O <=  KEY_EN_1(31 downto 0);
       when "01" =>
         visual_C12_O <=  KEY_EN_2(31 downto 0);
       when "10" =>
         visual_C12_O <=  KEY_EN_3(31 downto 0);
       when others =>
         visual_C12_O <=  KEY_EN_4(31 downto 0);
     end case;
   end process;
 
 
  KEY_DE(127 downto 96) <= DE_KEY1(31 downto 0);
  KEY_DE(95 downto 64) <= DE_KEY2(31 downto 0);
  KEY_DE(63 downto 32) <= DE_KEY3(31 downto 0);
  KEY_DE(31 downto 0) <= DE_KEY4(31 downto 0);
 
  KEY_EN_128(127 downto 0) <= (visual_C8_Q);
 
 
  process (CLK , RST)
  begin
   if (RST = '0') then
      visual_C8_Q <= (others => '0');
   elsif (CLK'event and CLK = '1') then
 
      if (E_128 = '1') then
        visual_C8_Q <= (KEY_EN(127 downto 0));
      end if;
 
  end if;
  end process;
 
end SUBKEY_DE_128;
----------------------------------------------------