rijndael_de_top.vhd

AES解密运算模块

       when '0' =>
         visual_C22_O <=  XORD_6(7 downto 0);
       when others =>
         visual_C22_O <=  Q(7 downto 0);
     end case;
   end process;
 
 
   S0(7 downto 0) <= ( AN2_0(7 downto 0)) and ( B(7 downto 0));
 
 
  AN2_0(7) <= A(0);
  AN2_0(6) <= A(0);
  AN2_0(5) <= A(0);
  AN2_0(4) <= A(0);
  AN2_0(3) <= A(0);
  AN2_0(2) <= A(0);
  AN2_0(1) <= A(0);
  AN2_0(0) <= A(0);
 
   S1(7 downto 0) <= ( AN2_1(7 downto 0)) and ( D(7 downto 0));
 
 
  AN2_1(7) <= A(1);
  AN2_1(6) <= A(1);
  AN2_1(5) <= A(1);
  AN2_1(4) <= A(1);
  AN2_1(3) <= A(1);
  AN2_1(2) <= A(1);
  AN2_1(1) <= A(1);
  AN2_1(0) <= A(1);
 
   S2(7 downto 0) <= ( AN2_2(7 downto 0)) and ( F(7 downto 0));
 
 
  AN2_2(7) <= A(2);
  AN2_2(6) <= A(2);
  AN2_2(5) <= A(2);
  AN2_2(4) <= A(2);
  AN2_2(3) <= A(2);
  AN2_2(2) <= A(2);
  AN2_2(1) <= A(2);
  AN2_2(0) <= A(2);
 
   S3(7 downto 0) <= ( AN2_3(7 downto 0)) and ( H(7 downto 0));
 
 
  AN2_3(7) <= A(3);
  AN2_3(6) <= A(3);
  AN2_3(5) <= A(3);
  AN2_3(4) <= A(3);
  AN2_3(3) <= A(3);
  AN2_3(2) <= A(3);
  AN2_3(1) <= A(3);
  AN2_3(0) <= A(3);
 
   S4(7 downto 0) <= ( AN2_4(7 downto 0)) and ( J(7 downto 0));
 
 
  AN2_4(7) <= A(4);
  AN2_4(6) <= A(4);
  AN2_4(5) <= A(4);
  AN2_4(4) <= A(4);
  AN2_4(3) <= A(4);
  AN2_4(2) <= A(4);
  AN2_4(1) <= A(4);
  AN2_4(0) <= A(4);
 
   S5(7 downto 0) <= ( AN2_5(7 downto 0)) and ( L(7 downto 0));
 
 
  AN2_5(7) <= A(5);
  AN2_5(6) <= A(5);
  AN2_5(5) <= A(5);
  AN2_5(4) <= A(5);
  AN2_5(3) <= A(5);
  AN2_5(2) <= A(5);
  AN2_5(1) <= A(5);
  AN2_5(0) <= A(5);
 
   S6(7 downto 0) <= ( AN2_6(7 downto 0)) and ( P(7 downto 0));
 
 
  AN2_6(7) <= A(6);
  AN2_6(6) <= A(6);
  AN2_6(5) <= A(6);
  AN2_6(4) <= A(6);
  AN2_6(3) <= A(6);
  AN2_6(2) <= A(6);
  AN2_6(1) <= A(6);
  AN2_6(0) <= A(6);
 
   S7(7 downto 0) <= ( AN2_7(7 downto 0)) and ( R(7 downto 0));
 
 
  AN2_7(7) <= A(7);
  AN2_7(6) <= A(7);
  AN2_7(5) <= A(7);
  AN2_7(4) <= A(7);
  AN2_7(3) <= A(7);
  AN2_7(2) <= A(7);
  AN2_7(1) <= A(7);
  AN2_7(0) <= A(7);
 
   T_0(7 downto 0) <= ( S0(7 downto 0)) xor ( S1(7 downto 0));
 
 
   T_1(7 downto 0) <= ( T_0(7 downto 0)) xor ( S2(7 downto 0));
 
 
   T_2(7 downto 0) <= ( T_1(7 downto 0)) xor ( S3(7 downto 0));
 
 
   T_3(7 downto 0) <= ( T_2(7 downto 0)) xor ( S4(7 downto 0));
 
 
   T_4(7 downto 0) <= ( T_3(7 downto 0)) xor ( S5(7 downto 0));
 
 
   T_5(7 downto 0) <= ( T_4(7 downto 0)) xor ( S6(7 downto 0));
 
 
   MPOLMUL8OUT(7 downto 0) <= ( T_5(7 downto 0)) xor ( S7(7 downto 0));
 
end MPOLMUL8;
----------------------------------------------------
--  
--  Library Name :  rijndael_min_new
--  Unit    Name :  KEY_DE_GEN
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_UNSIGNED.all;
entity KEY_DE_GEN is
  port (
        CLK : in std_logic;
        DA_CO_S : in std_logic_vector(1 downto 0 );
        DE_IN_E : in std_logic;
        DE_KEY : out std_logic_vector(31 downto 0 );
        DK32_E : in std_logic;
        E_DK1 : in std_logic;
        E_DK2 : in std_logic;
        E_DK3 : in std_logic;
        E_DK4 : in std_logic;
        E_MP1 : in std_logic;
        E_MP2 : in std_logic;
        E_MP3 : in std_logic;
        E_MP4 : in std_logic;
        KEY_EN : in std_logic_vector(31 downto 0 );
        RST : in std_logic;
        SECT_CON : in std_logic_vector(1 downto 0 )
        );
 
 
end KEY_DE_GEN;
 
 
use work.all;
architecture KEY_DE_GEN of KEY_DE_GEN is
 
  signal DE_kRY1 : std_logic_vector(7 downto 0 );
  signal DE_kRY2 : std_logic_vector(7 downto 0 );
  signal DE_kRY3 : std_logic_vector(7 downto 0 );
  signal DE_kRY4 : std_logic_vector(7 downto 0 );
  signal EK_IN : std_logic_vector(7 downto 0 );
  signal KEY_ENS : std_logic_vector(31 downto 0 );
  signal ks : std_logic_vector(31 downto 0 );
  signal M : std_logic_vector(6 downto 0 );
  signal MPOLMUL8_Q : std_logic_vector(7 downto 0 );
  signal MPOMUL_Q1 : std_logic_vector(7 downto 0 );
  signal MPOMUL_Q2 : std_logic_vector(7 downto 0 );
  signal MPOMUL_Q3 : std_logic_vector(7 downto 0 );
  signal MPOMUL_Q4 : std_logic_vector(7 downto 0 );
  signal S9 : std_logic_vector(7 downto 0 );
  signal Sb : std_logic_vector(7 downto 0 );
  signal Sd : std_logic_vector(7 downto 0 );
  signal Se : std_logic_vector(7 downto 0 );
  signal SEBD9_HH : std_logic_vector(7 downto 0 );
  signal SEBD9_HL : std_logic_vector(7 downto 0 );
  signal SEBD9_LH : std_logic_vector(7 downto 0 );
  signal SEBD9_LL : std_logic_vector(7 downto 0 );
  signal SEBD9_Q : std_logic_vector(7 downto 0 );
  signal XOR_Q : std_logic_vector(7 downto 0 );
  component MPOLMUL8
      port (
            A : in std_logic_vector(7 downto 0 );
            B : in std_logic_vector(7 downto 0 );
            M : in std_logic_vector(6 downto 0 );
            MPOLMUL8OUT : out std_logic_vector(7 downto 0 )
            );
  end component;
  signal visual_C37_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C39_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C40_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C41_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C42_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C43_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C44_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C45_Q : std_logic_vector(8 - 1 downto 0 );
  signal visual_C46_Q : std_logic_vector(32 - 1 downto 0 );
  signal visual_C1_O : std_logic_vector(8 - 1 downto 0 );
  signal visual_C12_O : std_logic_vector(8 - 1 downto 0 );
  signal visual_C13_O : std_logic_vector(8 - 1 downto 0 );
  signal visual_C14_O : std_logic_vector(8 - 1 downto 0 );
  signal visual_C32_O : std_logic_vector(8 - 1 downto 0 );
  signal visual_C33_Q : std_logic_vector(32 - 1 downto 0 );
  signal visual_C36_O : std_logic_vector(8 - 1 downto 0 );
 
  -- Start Configuration Specification
  -- ++ for all : MPOLMUL8 use entity work.MPOLMUL8(MPOLMUL8);
  -- End Configuration Specification
 
begin
 
  C34: MPOLMUL8
    port map (
              A => SEBD9_Q(7 downto 0),
              B => EK_IN(7 downto 0),
              M => M(6 downto 0),
              MPOLMUL8OUT => MPOLMUL8_Q(7 downto 0)
              );
 
  Se(7 downto 0) <= "00001110";
 
 
  Sb(7 downto 0) <= "00001011";
 
 
  Sd(7 downto 0) <= "00001101";
 
 
  S9(7 downto 0) <= "00001001";
 
 
  SEBD9_HH(7 downto 0) <= (visual_C1_O);
   process (Se , Sb , Sd , S9 , DA_CO_S)
   begin
     case DA_CO_S(1 downto 0) is
       when "00" =>
         visual_C1_O <=  Se(7 downto 0);
       when "01" =>
         visual_C1_O <=  Sb(7 downto 0);
       when "10" =>
         visual_C1_O <=  Sd(7 downto 0);
       when others =>
         visual_C1_O <=  S9(7 downto 0);
     end case;
   end process;
 
 
  SEBD9_HL(7 downto 0) <= (visual_C12_O);
   process (S9 , Se , Sb , Sd , DA_CO_S)
   begin
     case DA_CO_S(1 downto 0) is
       when "00" =>
         visual_C12_O <=  S9(7 downto 0);
       when "01" =>
         visual_C12_O <=  Se(7 downto 0);
       when "10" =>
         visual_C12_O <=  Sb(7 downto 0);
       when others =>
         visual_C12_O <=  Sd(7 downto 0);
     end case;
   end process;
 
 
  SEBD9_LH(7 downto 0) <= (visual_C13_O);
   process (Sd , S9 , Se , Sb , DA_CO_S)
   begin
     case DA_CO_S(1 downto 0) is
       when "00" =>
         visual_C13_O <=  Sd(7 downto 0);
       when "01" =>
         visual_C13_O <=  S9(7 downto 0);
       when "10" =>
         visual_C13_O <=  Se(7 downto 0);
       when others =>
         visual_C13_O <=  Sb(7 downto 0);
     end case;
   end process;
 
 
  SEBD9_LL(7 downto 0) <= (visual_C14_O);
   process (Sb , Sd , S9 , Se , DA_CO_S)
   begin
     case DA_CO_S(1 downto 0) is
       when "00" =>
         visual_C14_O <=  Sb(7 downto 0);
       when "01" =>
         visual_C14_O <=  Sd(7 downto 0);
       when "10" =>
         visual_C14_O <=  S9(7 downto 0);
       when others =>
         visual_C14_O <=  Se(7 downto 0);
     end case;
   end process;
 
 
  EK_IN(7 downto 0) <= (visual_C32_O);
   process (KEY_ENS , DA_CO_S)
   begin
     case DA_CO_S(1 downto 0) is
       when "00" =>
         visual_C32_O <=  KEY_ENS(31 downto 24);
       when "01" =>
         visual_C32_O <=  KEY_ENS(23 downto 16);
       when "10" =>
         visual_C32_O <=  KEY_ENS(15 downto 8);
       when others =>
         visual_C32_O <=  KEY_ENS(7 downto 0);
     end case;
   end process;
 
 
  KEY_ENS(31 downto 0) <= (visual_C33_Q);
 
 
  process (CLK , RST)
  begin
   if (RST = '0') then
      visual_C33_Q <= (others => '0');
   elsif (CLK'event and CLK = '1') then
 
      if (DE_IN_E = '1') then
        visual_C33_Q <= (KEY_EN(31 downto 0));
      end if;
 
  end if;
  end process;
 
 
  M(6 downto 0) <= "0001101";
 
 
  SEBD9_Q(7 downto 0) <= (visual_C36_O);
   process (SEBD9_HH , SEBD9_HL , SEBD9_LH , SEBD9_LL , SECT_CON)
   begin
     case SECT_CON(1 downto 0) is
       when "00" =>
         visual_C36_O <=  SEBD9_HH(7 downto 0);
       when "01" =>
         visual_C36_O <=  SEBD9_HL(7 downto 0);
       when "10" =>
         visual_C36_O <=  SEBD9_LH(7 downto 0);
       when others =>
         visual_C36_O <=  SEBD9_LL(7 downto 0);
     end case;
   end process;
 
 
  MPOMUL_Q1(7 downto 0) <= (visual_C37_Q);
 
 
  process (CLK , RST)
  begin
   if (RST = '0') then
      visual_C37_Q <= (others => '0');
   elsif (CLK'event and CLK = '1') then
 
      if (E_MP1 = '1') then
        visual_C37_Q <= (MPOLMUL8_Q(7 downto 0));
      end if;
 
  end if;
  end process;
 
 
   XOR_Q(7 downto 0) <= ( MPOMUL_Q1(7 downto 0)) xor ( MPOMUL_Q2(7 downto 0)) xor ( MPOMUL_Q3(7 downto 0)) xor ( MPOMUL_Q4(7 downto 0));
 
 
  MPOMUL_Q2(7 downto 0) <= (visual_C39_Q);
 
 
  process (CLK , RST)
  begin
   if (RST = '0') then
      visual_C39_Q <= (others => '0');
   elsif (CLK'event and CLK = '1') then
 
      if (E_MP2 = '1') then
        visual_C39_Q <= (MPOLMUL8_Q(7 downto 0));
      end if;
 
  end if;
  end process;
 
 
  MPOMUL_Q3(7 downto 0) <= (visual_C40_Q);
 
 
  process (CLK , RST)
  begin
   if (RST = '0') then
      visual_C40_Q <= (others => '0');
   elsif (CLK'event and CLK = '1') then
 
      if (E_MP3 = '1') then
        visual_C40_Q <= (MPOLMUL8_Q(7 downto 0));
      end if;
 
  end if;
  end process;
 
 
  MPOMUL_Q4(7 downto 0) <= (visual_C41_Q);
 
 
  process (CLK , RST)
  begin
   if (RST = '0') then
      visual_C41_Q <= (others => '0');
   elsif (CLK'event and CLK = '1') then
 
      if (E_MP4 = '1') then
        visual_C41_Q <= (MPOLMUL8_Q(7 downto 0));
      end if;
 
  end if;
  end process;
 
 
  DE_kRY1(7 downto 0) <= (visual_C42_Q);
 
 
  process (CLK , RST)
  begin
   if (RST = '0') then
      visual_C42_Q <= (others => '0');
   elsif (CLK'event and CLK = '1') then
 
      if (E_DK1 = '1') then
        visual_C42_Q <= (XOR_Q(7 downto 0));
      end if;
 
  end if;
  end process;
 
 
  DE_kRY2(7 downto 0) <= (visual_C43_Q);
 
 
  process (CLK , RST)
  begin
   if (RST = '0') then
      visual_C43_Q <= (others => '0');
   elsif (CLK'event and CLK = '1') then
 
      if (E_DK2 = '1') then
        visual_C43_Q <= (XOR_Q(7 downto 0));
      end if;
 
  end if;
  end process;
 
 
  DE_kRY3(7 downto 0) <= (visual_C44_Q);
 
 
  process (CLK , RST)
  begin
   if (RST = '0') then
      visual_C44_Q <= (others => '0');
   elsif (CLK'event and CLK = '1') then
 
      if (E_DK3 = '1') then
        visual_C44_Q <= (XOR_Q(7 downto 0));
      end if;
 
  end if;
  end process;
 
 
  DE_kRY4(7 downto 0) <= (visual_C45_Q);
 
 
  process (CLK , RST)
  begin
   if (RST = '0') then
      visual_C45_Q <= (others => '0');
   elsif (CLK'event and CLK = '1') then
 
      if (E_DK4 = '1') then
        visual_C45_Q <= (XOR_Q(7 downto 0));
      end if;
 
  end if;
  end process;
 
 
  ks(31 downto 24) <= DE_kRY1(7 downto 0);
  ks(23 downto 16) <= DE_kRY2(7 downto 0);
  ks(15 downto 8) <= DE_kRY3(7 downto 0);
  ks(7 downto 0) <= DE_kRY4(7 downto 0);
 
  DE_KEY(31 downto 0) <= (visual_C46_Q);
 
 
  process (CLK , RST)
  begin
   if (RST = '0') then
      visual_C46_Q <= (others => '0');
   elsif (CLK'event and CLK = '1') then
 
      if (DK32_E = '1') then
        visual_C46_Q <= (ks(31 downto 0));
      end if;
 
  end if;
  end process;
 
end KEY_DE_GEN;
----------------------------------------------------
--  
--  Library Name :  rijndael_min_new
--  Unit    Name :  MIXCOLUMN_DE
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use ieee.STD_LOGIC_UNSIGNED.all;
entity MIXCOLUMN_DE is
  port (
        CLK : in std_logic;
        DE_KEY : out std_logic_vector(31 downto 0 );