idea_de_top.vhd

IDEA解密运算模块

              E_MMUL16A1_IN<='1';
              KEY_BUSY<='1';
              visual_S0_current <= S1;
            else
              visual_S0_current <= S0;
            end if;
 
          when S1 =>
            if (DEK_SELM = "10001") then
              E_MMUL16A1_IN<='0';
              visual_S0_current <= S3;
            elsif (MMUL16A1_INOV = '1') then
              E_MMUL16A1_IN<='1';
              DEK_SELM<=DEK_SELM+1;
              visual_S0_current <= S1;
            else
              E_MMUL16A1_IN<='0';
              visual_S0_current <= S1;
            end if;
 
          when S3 =>
            if (MMUL16A1_INOV = '1') then
              E_MMUL16A1_IN<='0';
              DEK_SELM<="00000";
              KEY_BUSY<='0';
              visual_S0_current <= S0;
            else
              visual_S0_current <= S3;
            end if;
 
          when others =>
 
            E_MMUL16A1_IN<='0';
            DEK_SELM<="00000";
            KEY_BUSY<='0';
            visual_S0_current <= S0;
        end case;
      end if;
    end if;
  end process;
 
 
  DEK_SEL<=DEK_SELM;
end DE_KEY_CTRL;
----------------------------------------------------
--  
--  Library Name :  Idea_vhd_100M
--  Unit    Name :  DE_KEY_GEN
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
entity DE_KEY_GEN is
  port (
        CLK : in std_logic;
        EKLD : in std_logic;
        KEY_BUSY : out std_logic;
        KEY_IN : in std_logic_vector(127 downto 0 );
        RST : in std_logic;
        ZY_BUS_1 : out std_logic_vector(95 downto 0 );
        ZY_BUS_2 : out std_logic_vector(95 downto 0 );
        ZY_BUS_3 : out std_logic_vector(95 downto 0 );
        ZY_BUS_4 : out std_logic_vector(95 downto 0 );
        ZY_BUS_5 : out std_logic_vector(95 downto 0 );
        ZY_BUS_6 : out std_logic_vector(95 downto 0 );
        ZY_BUS_7 : out std_logic_vector(95 downto 0 );
        ZY_BUS_8 : out std_logic_vector(95 downto 0 );
        ZY_BUS_9 : out std_logic_vector(63 downto 0 )
        );
 
 
end DE_KEY_GEN;
 
 
use work.all;
architecture DE_KEY_GEN of DE_KEY_GEN is
 
  signal DEK_SEL : std_logic_vector(4 downto 0 );
  signal E1 : std_logic;
  signal E2 : std_logic;
  signal E_K : std_logic;
  signal MADD16_1 : std_logic_vector(15 downto 0 );
  signal MADD16OUT1 : std_logic_vector(15 downto 0 );
  signal MADD18_1 : std_logic_vector(15 downto 0 );
  signal MADD2_1 : std_logic_vector(15 downto 0 );
  signal MMUL18_1 : std_logic_vector(15 downto 0 );
  signal MMUL_16A1INQQ : std_logic_vector(15 downto 0 );
  signal MULL16_1 : std_logic_vector(15 downto 0 );
  signal MULL2_1 : std_logic_vector(15 downto 0 );
  signal S10 : std_logic_vector(1 downto 0 );
  signal S11 : std_logic_vector(4 downto 0 );
  signal S12 : std_logic_vector(10 downto 0 );
  signal S13 : std_logic_vector(11 downto 0 );
  signal S14 : std_logic_vector(3 downto 0 );
  signal S16 : std_logic_vector(12 downto 0 );
  signal S17 : std_logic_vector(2 downto 0 );
  signal S7 : std_logic_vector(8 downto 0 );
  signal S8 : std_logic_vector(6 downto 0 );
  signal S9 : std_logic_vector(13 downto 0 );
  signal Y1 : std_logic_vector(15 downto 0 );
  signal Y10 : std_logic_vector(15 downto 0 );
  signal Y13 : std_logic_vector(15 downto 0 );
  signal Y14 : std_logic_vector(15 downto 0 );
  signal Y15 : std_logic_vector(15 downto 0 );
  signal Y16 : std_logic_vector(15 downto 0 );
  signal Y19 : std_logic_vector(15 downto 0 );
  signal Y2 : std_logic_vector(15 downto 0 );
  signal Y20 : std_logic_vector(15 downto 0 );
  signal Y21 : std_logic_vector(15 downto 0 );
  signal Y22 : std_logic_vector(15 downto 0 );
  signal Y25 : std_logic_vector(15 downto 0 );
  signal Y26 : std_logic_vector(15 downto 0 );
  signal Y27 : std_logic_vector(15 downto 0 );
  signal Y28 : std_logic_vector(15 downto 0 );
  signal Y3 : std_logic_vector(15 downto 0 );
  signal Y31 : std_logic_vector(15 downto 0 );
  signal Y32 : std_logic_vector(15 downto 0 );
  signal Y33 : std_logic_vector(15 downto 0 );
  signal Y34 : std_logic_vector(15 downto 0 );
  signal Y37 : std_logic_vector(15 downto 0 );
  signal Y38 : std_logic_vector(15 downto 0 );
  signal Y39 : std_logic_vector(15 downto 0 );
  signal Y4 : std_logic_vector(15 downto 0 );
  signal Y40 : std_logic_vector(15 downto 0 );
  signal Y43 : std_logic_vector(15 downto 0 );
  signal Y44 : std_logic_vector(15 downto 0 );
  signal Y45 : std_logic_vector(15 downto 0 );
  signal Y46 : std_logic_vector(15 downto 0 );
  signal Y49 : std_logic_vector(15 downto 0 );
  signal Y50 : std_logic_vector(15 downto 0 );
  signal Y51 : std_logic_vector(15 downto 0 );
  signal Y52 : std_logic_vector(15 downto 0 );
  signal Y7 : std_logic_vector(15 downto 0 );
  signal Y8 : std_logic_vector(15 downto 0 );
  signal Y9 : std_logic_vector(15 downto 0 );
  signal Z1 : std_logic_vector(15 downto 0 );
  signal Z10 : std_logic_vector(15 downto 0 );
  signal Z11 : std_logic_vector(15 downto 0 );
  signal Z12 : std_logic_vector(15 downto 0 );
  signal Z13 : std_logic_vector(15 downto 0 );
  signal Z14 : std_logic_vector(15 downto 0 );
  signal Z15 : std_logic_vector(15 downto 0 );
  signal Z16 : std_logic_vector(15 downto 0 );
  signal Z17 : std_logic_vector(15 downto 0 );
  signal Z18 : std_logic_vector(15 downto 0 );
  signal Z19 : std_logic_vector(15 downto 0 );
  signal Z2 : std_logic_vector(15 downto 0 );
  signal Z20 : std_logic_vector(15 downto 0 );
  signal Z21 : std_logic_vector(15 downto 0 );
  signal Z22 : std_logic_vector(15 downto 0 );
  signal Z23 : std_logic_vector(15 downto 0 );
  signal Z24 : std_logic_vector(15 downto 0 );
  signal Z25 : std_logic_vector(15 downto 0 );
  signal Z26 : std_logic_vector(15 downto 0 );
  signal Z27 : std_logic_vector(15 downto 0 );
  signal Z28 : std_logic_vector(15 downto 0 );
  signal Z29 : std_logic_vector(15 downto 0 );
  signal Z3 : std_logic_vector(15 downto 0 );
  signal Z30 : std_logic_vector(15 downto 0 );
  signal Z31 : std_logic_vector(15 downto 0 );
  signal Z32 : std_logic_vector(15 downto 0 );
  signal Z33 : std_logic_vector(15 downto 0 );
  signal Z34 : std_logic_vector(15 downto 0 );
  signal Z35 : std_logic_vector(15 downto 0 );
  signal Z36 : std_logic_vector(15 downto 0 );
  signal Z37 : std_logic_vector(15 downto 0 );
  signal Z38 : std_logic_vector(15 downto 0 );
  signal Z39 : std_logic_vector(15 downto 0 );
  signal Z4 : std_logic_vector(15 downto 0 );
  signal Z40 : std_logic_vector(15 downto 0 );
  signal Z41 : std_logic_vector(15 downto 0 );
  signal Z42 : std_logic_vector(15 downto 0 );
  signal Z43 : std_logic_vector(15 downto 0 );
  signal Z44 : std_logic_vector(15 downto 0 );
  signal Z45 : std_logic_vector(15 downto 0 );
  signal Z46 : std_logic_vector(15 downto 0 );
  signal Z47 : std_logic_vector(15 downto 0 );
  signal Z48 : std_logic_vector(15 downto 0 );
  signal Z49 : std_logic_vector(15 downto 0 );
  signal Z5 : std_logic_vector(15 downto 0 );
  signal Z50 : std_logic_vector(15 downto 0 );
  signal Z51 : std_logic_vector(15 downto 0 );
  signal Z52 : std_logic_vector(15 downto 0 );
  signal Z6 : std_logic_vector(15 downto 0 );
  signal Z7 : std_logic_vector(15 downto 0 );
  signal Z8 : std_logic_vector(15 downto 0 );
  signal Z9 : std_logic_vector(15 downto 0 );
  component DE_KEY_CTRL
      port (
            E_K : in std_logic;
            CLK : in std_logic;
            RST : in std_logic;
            E_MMUL16A1_IN : out std_logic;
            MMUL16A1_INOV : in std_logic;
            DEK_SEL : out std_logic_vector(4 downto 0 );
            KEY_BUSY : out std_logic
            );
  end component;
  component E_K_CTRL
      port (
            EKLD : in std_logic;
            CLK : in std_logic;
            RST : in std_logic;
            E_K : out std_logic
            );
  end component;
  component MMUL_16A1_IN
      port (
            CLK : in std_logic;
            D : in std_logic_vector(15 downto 0 );
            E : in std_logic;
            OV : out std_logic;
            Q : out std_logic_vector(15 downto 0 );
            RST : in std_logic
            );
  end component;
  component MADD16_IN
      port (
            D : in std_logic_vector(15 downto 0 );
            Q : out std_logic_vector(15 downto 0 )
            );
  end component;
  signal visual_C18_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C19_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C21_O : std_logic_vector(16 - 1 downto 0 );
  signal visual_C22_O : std_logic_vector(16 - 1 downto 0 );
  signal visual_C23_O : std_logic_vector(16 - 1 downto 0 );
  signal visual_C0_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C1_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C3_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C4_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C5_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C6_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C7_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C9_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C10_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C11_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C12_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C13_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C14_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C15_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C16_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C17_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C124_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C125_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C24_O : std_logic_vector(16 - 1 downto 0 );
  signal visual_C33_O : std_logic_vector(16 - 1 downto 0 );
  signal visual_C34_O : std_logic_vector(16 - 1 downto 0 );
  signal visual_C108_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C109_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C111_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C112_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C113_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C114_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C115_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C116_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C106_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C107_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C117_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C118_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C119_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C120_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C122_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C123_Q : std_logic_vector(16 - 1 downto 0 );
 
  -- Start Configuration Specification
  -- ++ for all : DE_KEY_CTRL use entity work.DE_KEY_CTRL(DE_KEY_CTRL);
  -- ++ for all : E_K_CTRL use entity work.E_K_CTRL(E_K_CTRL);
  -- ++ for all : MMUL_16A1_IN use entity work.MMUL_16A1_IN(MMUL_16A1_IN);
  -- ++ for all : MADD16_IN use entity work.MADD16_IN(MADD16_IN);
  -- End Configuration Specification
 
begin
 
  C20: DE_KEY_CTRL
    port map (
              E_K => E_K,
              CLK => CLK,
              RST => RST,
              E_MMUL16A1_IN => E2,
              MMUL16A1_INOV => E1,
              DEK_SEL => DEK_SEL(4 downto 0),
              KEY_BUSY => KEY_BUSY
              );
 
  C25: E_K_CTRL
    port map (
              EKLD => EKLD,
              CLK => CLK,
              RST => RST,
              E_K => E_K
              );
 
  MA7: MMUL_16A1_IN
    port map (
              CLK => CLK,
              D => MMUL18_1(15 downto 0),
              E => E2,
              OV => E1,
              Q => MMUL_16A1INQQ(15 downto 0),
              RST => RST
              );
 
  C155: MADD16_IN
    port map (
              D => MADD18_1(15 downto 0),
              Q => MADD16OUT1(15 downto 0)
              );
 
  Z8(15 downto 0) <= KEY_IN(15 downto 0);
  Z7(15 downto 0) <= KEY_IN(31 downto 16);
  Z6(15 downto 0) <= KEY_IN(47 downto 32);
  Z5(15 downto 0) <= KEY_IN(63 downto 48);
  Z4(15 downto 0) <= KEY_IN(79 downto 64);
  Z3(15 downto 0) <= KEY_IN(95 downto 80);
  Z2(15 downto 0) <= KEY_IN(111 downto 96);
  Z1(15 downto 0) <= KEY_IN(127 downto 112);
 
  Z16(15 downto 0) <= KEY_IN(118 downto 103);
  Z13(15 downto 0) <= KEY_IN(38 downto 23);
  Z12(15 downto 0) <= KEY_IN(54 downto 39);
  Z11(15 downto 0) <= KEY_IN(70 downto 55);
  Z14(15 downto 0) <= KEY_IN(22 downto 7);
  Z10(15 downto 0) <= KEY_IN(86 downto 71);
  Z9(15 downto 0) <= KEY_IN(102 downto 87);
  S7(8 downto 0) <= KEY_IN(127 downto 119);
  S8(6 downto 0) <= KEY_IN(6 downto 0);
 
  Z15(15 downto 9) <= S8(6 downto 0);
  Z15(8 downto 0) <= S7(8 downto 0);
 
  Z24(15 downto 0) <= KEY_IN(93 downto 78);
  Z20(15 downto 0) <= KEY_IN(29 downto 14);
  Z19(15 downto 0) <= KEY_IN(45 downto 30);
  Z18(15 downto 0) <= KEY_IN(61 downto 46);
  Z17(15 downto 0) <= KEY_IN(77 downto 62);
  Z23(15 downto 0) <= KEY_IN(109 downto 94);
  Z22(15 downto 0) <= KEY_IN(125 downto 110);
  S9(13 downto 0) <= KEY_IN(13 downto 0);
  S10(1 downto 0) <= KEY_IN(127 downto 126);
 
  Z21(15 downto 2) <= S9(13 downto 0);
  Z21(1 downto 0) <= S10(1 downto 0);
 
  Z29(15 downto 0) <= KEY_IN(116 downto 101);
  S12(10 downto 0) <= KEY_IN(127 downto 117);
  S11(4 downto 0) <= KEY_IN(4 downto 0);
  Z31(15 downto 0) <= KEY_IN(84 downto 69);
  Z30(15 downto 0) <= KEY_IN(100 downto 85);
  Z27(15 downto 0) <= KEY_IN(20 downto 5);
  Z26(15 downto 0) <= KEY_IN(36 downto 21);
  Z32(15 downto 0) <= KEY_IN(68 downto 53);
  Z25(15 downto 0) <= KEY_IN(52 downto 37);
 
  Z28(15 downto 11) <= S11(4 downto 0);
  Z28(10 downto 0) <= S12(10 downto 0);
 
  Z40(15 downto 0) <= KEY_IN(43 downto 28);
  Z39(15 downto 0) <= KEY_IN(59 downto 44);
  Z38(15 downto 0) <= KEY_IN(75 downto 60);
  Z37(15 downto 0) <= KEY_IN(91 downto 76);
  Z36(15 downto 0) <= KEY_IN(107 downto 92);
  Z35(15 downto 0) <= KEY_IN(123 downto 108);
  S14(3 downto 0) <= KEY_IN(127 downto 124);
  S13(11 downto 0) <= KEY_IN(11 downto 0);
  Z33(15 downto 0) <= KEY_IN(27 downto 12);
 
  Z34(15 downto 4) <= S13(11 downto 0);
  Z34(3 downto 0) <= S14(3 downto 0);
 
  Z48(15 downto 0) <= KEY_IN(18 downto 3);
  Z47(15 downto 0) <= KEY_IN(34 downto 19);
  Z46(15 downto 0) <= KEY_IN(50 downto 35);
  Z45(15 downto 0) <= KEY_IN(66 downto 51);
  Z44(15 downto 0) <= KEY_IN(82 downto 67);
  Z43(15 downto 0) <= KEY_IN(98 downto 83);
  Z42(15 downto 0) <= KEY_IN(114 downto 99);
  S16(12 downto 0) <= KEY_IN(127 downto 115);
  S17(2 downto 0) <= KEY_IN(2 downto 0);
 
  Z41(15 downto 13) <= S17(2 downto 0);
  Z41(12 downto 0) <= S16(12 downto 0);
 
  Z52(15 downto 0) <= KEY_IN(57 downto 42);
  Z51(15 downto 0) <= KEY_IN(73 downto 58);
  Z50(15 downto 0) <= KEY_IN(89 downto 74);
  Z49(15 downto 0) <= KEY_IN(105 downto 90);
 
  Y49(15 downto 0) <= (visual_C18_Q);
 
 
  process (CLK)
  begin
  if (CLK'event and CLK = '1') then
    if (RST = '0') then
      visual_C18_Q <= (others => '0');
    else
      if (E1 = '1') then
        visual_C18_Q <= (Y52(15 downto 0));
      end if;
   end if;
  end if;
  end process;
 
 
  Y52(15 downto 0) <= (visual_C19_Q);
 
 
  process (CLK)
  begin
  if (CLK'event and CLK = '1') then
    if (RST = '0') then
      visual_C19_Q <= (others => '0');
    else
      if (E1 = '1') then
        visual_C19_Q <= (MMUL_16A1INQQ(15 downto 0));
      end if;
   end if;
  end if;
  end process;
 
 
  MULL16_1(15 downto 0) <= (visual_C21_O);
   process (Z49 , Z52 , Z43 , Z46 , Z37 , Z40 , Z31 , Z34 , Z25
             , Z28 , Z19 , Z22 , Z13 , Z16 , Z7 , Z10 , DEK_SEL)
   begin
     case DEK_SEL(3 downto 0) is
       when "0000" =>
         visual_C21_O <=  Z49(15 downto 0);
       when "0001" =>
         visual_C21_O <=  Z52(15 downto 0);
       when "0010" =>
         visual_C21_O <=  Z43(15 downto 0);
       when "0011" =>
         visual_C21_O <=  Z46(15 downto 0);
       when "0100" =>
         visual_C21_O <=  Z37(15 downto 0);
       when "0101" =>
         visual_C21_O <=  Z40(15 downto 0);
       when "0110" =>
         visual_C21_O <=  Z31(15 downto 0);
       when "0111" =>
         visual_C21_O <=  Z34(15 downto 0);
       when "1000" =>
         visual_C21_O <=  Z25(15 downto 0);
       when "1001" =>
         visual_C21_O <=  Z28(15 downto 0);
       when "1010" =>
         visual_C21_O <=  Z19(15 downto 0);
       when "1011" =>
         visual_C21_O <=  Z22(15 downto 0);
       when "1100" =>
         visual_C21_O <=  Z13(15 downto 0);
       when "1101" =>
         visual_C21_O <=  Z16(15 downto 0);
       when "1110" =>
         visual_C21_O <=  Z7(15 downto 0);
       when others =>
         visual_C21_O <=  Z10(15 downto 0);
     end case;
   end process;
 
 
  MULL2_1(15 downto 0) <= (visual_C22_O);
   process (Z1 , Z4 , DEK_SEL)
   begin
     case DEK_SEL(0) is
       when '0' =>
         visual_C22_O <=  Z1(15 downto 0);
       when others =>
         visual_C22_O <=  Z4(15 downto 0);
     end case;
   end process;
 
 
  MMUL18_1(15 downto 0) <= (visual_C23_O);
   process (MULL16_1 , MULL2_1 , DEK_SEL)
   begin
     case DEK_SEL(4) is
       when '0' =>
         visual_C23_O <=  MULL16_1(15 downto 0);
       when others =>
         visual_C23_O <=  MULL2_1(15 downto 0);
     end case;
   end process;
 
 
  Y46(15 downto 0) <= (visual_C0_Q);
 
 
  process (CLK)
  begin
  if (CLK'event and CLK = '1') then
    if (RST = '0') then
      visual_C0_Q <= (others => '0');
    else
      if (E1 = '1') then
        visual_C0_Q <= (Y49(15 downto 0));
      end if;
   end if;
  end if;
  end process;
 
 
  Y34(15 downto 0) <= (visual_C1_Q);
 
 
  process (CLK)