idea_de_top.vhd

IDEA解密运算模块

  S35(1) <= TJ1;
  S35(0) <= TJ3;
 
  S38 <= '0';
 
end MMUL_16A1_IN_1;
----------------------------------------------------
--  
--  Library Name :  Idea_vhd_100M
--  Unit    Name :  MMUL_16A1_IN
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
entity MMUL_16A1_IN is
  port (
        CLK : in std_logic;
        D : in std_logic_vector(15 downto 0 );
        E : in std_logic;
        OV : out std_logic;
        Q : out std_logic_vector(15 downto 0 );
        RST : in std_logic
        );
 
 
end MMUL_16A1_IN;
 
 
use work.all;
architecture MMUL_16A1_IN of MMUL_16A1_IN is
 
  signal A1_1 : std_logic_vector(16 downto 0 );
  signal A2_1 : std_logic_vector(16 downto 0 );
  signal CT : std_logic;
  signal E1 : std_logic;
  signal I1 : std_logic_vector(16 downto 0 );
  signal N1_1 : std_logic_vector(16 downto 0 );
  signal N2_1 : std_logic_vector(16 downto 0 );
  signal O : std_logic_vector(16 downto 0 );
  signal OV_1 : std_logic;
  signal OV_2 : std_logic;
  signal OV_S : std_logic;
  signal S105 : std_logic_vector(16 downto 0 );
  signal S106 : std_logic_vector(16 downto 0 );
  signal S108 : std_logic_vector(16 downto 0 );
  signal S110 : std_logic_vector(16 downto 0 );
  signal S113 : std_logic;
  signal S114 : std_logic;
  signal S19 : std_logic_vector(16 downto 0 );
  signal S21 : std_logic_vector(16 downto 0 );
  signal S25 : std_logic_vector(16 downto 0 );
  signal S27 : std_logic_vector(16 downto 0 );
  signal S29 : std_logic_vector(16 downto 0 );
  signal S39 : std_logic_vector(16 downto 0 );
  signal S42 : std_logic_vector(16 downto 0 );
  signal S54 : std_logic_vector(16 downto 0 );
  signal S64 : std_logic;
  signal S66 : std_logic;
  signal S69 : std_logic;
  signal S71 : std_logic;
  signal S73 : std_logic;
  signal S74 : std_logic;
  signal S81 : std_logic_vector(16 downto 0 );
  signal S82 : std_logic;
  signal S84 : std_logic_vector(16 downto 0 );
  component MMUL_16A1_IN_CT
      port (
            CLK : in std_logic;
            RST : in std_logic;
            OV_S : in std_logic;
            CT : out std_logic;
            E : in std_logic;
            E1 : out std_logic;
            OV : out std_logic
            );
  end component;
  component MMUL_16A1_IN_2
      port (
            A1 : in std_logic_vector(16 downto 0 );
            A1_1 : out std_logic_vector(16 downto 0 );
            A2 : in std_logic_vector(16 downto 0 );
            N1 : in std_logic_vector(16 downto 0 );
            N2 : in std_logic_vector(16 downto 0 );
            N2_1 : out std_logic_vector(16 downto 0 );
            OV : out std_logic;
            OV1 : in std_logic;
            OV2 : in std_logic;
            OV_1 : out std_logic;
            OV_2 : out std_logic;
            Q : out std_logic_vector(15 downto 0 );
            A2_1 : out std_logic_vector(16 downto 0 );
            N1_1 : out std_logic_vector(16 downto 0 )
            );
  end component;
  component MMUL_16A1_IN_1
      port (
            A1 : in std_logic_vector(16 downto 0 );
            A1_1 : out std_logic_vector(16 downto 0 );
            A2 : in std_logic_vector(16 downto 0 );
            N1 : in std_logic_vector(16 downto 0 );
            N2 : in std_logic_vector(16 downto 0 );
            N2_1 : out std_logic_vector(16 downto 0 );
            OV1 : in std_logic;
            OV2 : in std_logic;
            OV_1 : out std_logic;
            OV_2 : out std_logic;
            A2_1 : out std_logic_vector(16 downto 0 );
            N1_1 : out std_logic_vector(16 downto 0 )
            );
  end component;
  signal visual_C25_Q : std_logic;
  signal visual_C26_Q : std_logic;
  signal visual_C27_O : std_logic;
  signal visual_C28_O : std_logic;
  signal visual_C8_O : std_logic_vector(17 - 1 downto 0 );
  signal visual_C9_O : std_logic_vector(17 - 1 downto 0 );
  signal visual_C10_O : std_logic_vector(17 - 1 downto 0 );
  signal visual_C11_O : std_logic_vector(17 - 1 downto 0 );
  signal visual_C12_Q : std_logic_vector(17 - 1 downto 0 );
  signal visual_C13_Q : std_logic_vector(17 - 1 downto 0 );
  signal visual_C14_Q : std_logic_vector(17 - 1 downto 0 );
  signal visual_C15_Q : std_logic_vector(17 - 1 downto 0 );
 
  -- Start Configuration Specification
  -- ++ for all : MMUL_16A1_IN_CT use entity work.MMUL_16A1_IN_CT(
  -- ++   MMUL_16A1_IN_CT);
  -- ++ for all : MMUL_16A1_IN_2 use entity work.MMUL_16A1_IN_2(MMUL_16A1_IN_2);
  -- ++ for all : MMUL_16A1_IN_1 use entity work.MMUL_16A1_IN_1(MMUL_16A1_IN_1);
  -- End Configuration Specification
 
begin
 
  C29: MMUL_16A1_IN_CT
    port map (
              CLK => CLK,
              RST => RST,
              OV_S => OV_S,
              CT => CT,
              E => E,
              E1 => E1,
              OV => OV
              );
 
  C39: MMUL_16A1_IN_2
    port map (
              A1 => S105(16 downto 0),
              A1_1 => A1_1(16 downto 0),
              A2 => S108(16 downto 0),
              N1 => S110(16 downto 0),
              N2 => S106(16 downto 0),
              N2_1 => N2_1(16 downto 0),
              OV => OV_S,
              OV1 => S113,
              OV2 => S114,
              OV_1 => OV_1,
              OV_2 => OV_2,
              Q => Q(15 downto 0),
              A2_1 => A2_1(16 downto 0),
              N1_1 => N1_1(16 downto 0)
              );
 
  C35: MMUL_16A1_IN_1
    port map (
              A1 => S39(16 downto 0),
              A1_1 => S105(16 downto 0),
              A2 => S54(16 downto 0),
              N1 => S42(16 downto 0),
              N2 => S84(16 downto 0),
              N2_1 => S106(16 downto 0),
              OV1 => S66,
              OV2 => S71,
              OV_1 => S113,
              OV_2 => S114,
              A2_1 => S108(16 downto 0),
              N1_1 => S110(16 downto 0)
              );
 
  O(16 downto 0) <= (visual_C8_O);
   process (I1 , A1_1 , CT)
   begin
     case CT is
       when '0' =>
         visual_C8_O <=  I1(16 downto 0);
       when others =>
         visual_C8_O <=  A1_1(16 downto 0);
     end case;
   end process;
 
 
  S21(16 downto 0) <= (visual_C9_O);
   process (S19 , N2_1 , CT)
   begin
     case CT is
       when '0' =>
         visual_C9_O <=  S19(16 downto 0);
       when others =>
         visual_C9_O <=  N2_1(16 downto 0);
     end case;
   end process;
 
 
  S25(16 downto 0) <= (visual_C10_O);
   process (S81 , N1_1 , CT)
   begin
     case CT is
       when '0' =>
         visual_C10_O <=  S81(16 downto 0);
       when others =>
         visual_C10_O <=  N1_1(16 downto 0);
     end case;
   end process;
 
 
  S29(16 downto 0) <= (visual_C11_O);
   process (S27 , A2_1 , CT)
   begin
     case CT is
       when '0' =>
         visual_C11_O <=  S27(16 downto 0);
       when others =>
         visual_C11_O <=  A2_1(16 downto 0);
     end case;
   end process;
 
 
  S39(16 downto 0) <= (visual_C12_Q);
 
 
  process (CLK)
  begin
  if (CLK'event and CLK = '1') then
    if (RST = '0') then
      visual_C12_Q <= (others => '0');
    else
      if (E1 = '1') then
        visual_C12_Q <= (O(16 downto 0));
      end if;
   end if;
  end if;
  end process;
 
 
  S84(16 downto 0) <= (visual_C13_Q);
 
 
  process (CLK)
  begin
  if (CLK'event and CLK = '1') then
    if (RST = '0') then
      visual_C13_Q <= (others => '0');
    else
      if (E1 = '1') then
        visual_C13_Q <= (S21(16 downto 0));
      end if;
   end if;
  end if;
  end process;
 
 
  S42(16 downto 0) <= (visual_C14_Q);
 
 
  process (CLK)
  begin
  if (CLK'event and CLK = '1') then
    if (RST = '0') then
      visual_C14_Q <= (others => '0');
    else
      if (E1 = '1') then
        visual_C14_Q <= (S25(16 downto 0));
      end if;
   end if;
  end if;
  end process;
 
 
  S54(16 downto 0) <= (visual_C15_Q);
 
 
  process (CLK)
  begin
  if (CLK'event and CLK = '1') then
    if (RST = '0') then
      visual_C15_Q <= (others => '0');
    else
      if (E1 = '1') then
        visual_C15_Q <= (S29(16 downto 0));
      end if;
   end if;
  end if;
  end process;
 
 
  I1(16 downto 0) <= "00000000000000001";
 
 
  S27(16 downto 0) <= "00000000000000000";
 
 
  S19(16 downto 0) <= "10000000000000001";
 
 
  S81(16) <= S82;
  S81(15 downto 0) <= D(15 downto 0);
 
  S82 <= '0';
 
 
  S66 <= (visual_C25_Q);
 
 
  process (CLK)
  begin
  if (CLK'event and CLK = '1') then
    if (RST = '0') then
      visual_C25_Q <= '0';
    else
      if (E1 = '1') then
        visual_C25_Q <= (S69);
      end if;
   end if;
  end if;
  end process;
 
 
  S71 <= (visual_C26_Q);
 
 
  process (CLK)
  begin
  if (CLK'event and CLK = '1') then
    if (RST = '0') then
      visual_C26_Q <= '0';
    else
      if (E1 = '1') then
        visual_C26_Q <= (S64);
      end if;
   end if;
  end if;
  end process;
 
 
  S69 <= (visual_C27_O);
   process (S73 , OV_1 , CT)
   begin
     case CT is
       when '0' =>
         visual_C27_O <=  S73;
       when others =>
         visual_C27_O <=  OV_1;
     end case;
   end process;
 
 
  S64 <= (visual_C28_O);
   process (S74 , OV_2 , CT)
   begin
     case CT is
       when '0' =>
         visual_C28_O <=  S74;
       when others =>
         visual_C28_O <=  OV_2;
     end case;
   end process;
 
 
  S73 <= '1';
 
 
  S74 <= '1';
 
end MMUL_16A1_IN;
----------------------------------------------------
--  
--  Library Name :  Idea_vhd_100M
--  Unit    Name :  E_K_CTRL
--  Unit    Type :  State Machine
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_UNSIGNED.all;
entity E_K_CTRL is
  port (
        EKLD : in std_logic;
        CLK : in std_logic;
        RST : in std_logic;
        E_K : out std_logic
        );
 
end E_K_CTRL;
 
 
architecture E_K_CTRL of E_K_CTRL is
 
  type visual_S0_states is (S0, S1, S2);
  signal visual_S0_current : visual_S0_states;
 
 
begin
 
 
 
  -- Synchronous process
  E_K_CTRL_S0:
  process (CLK, RST)
  begin
 
    if (RST = '0') then
      E_K<='0';
      visual_S0_current <= S0;
    elsif (CLK'event and CLK = '1') then
      if (RST = '0') then
        E_K<='0';
        visual_S0_current <= S0;
      else
 
        case visual_S0_current is
          when S0 =>
            if (EKLD = '1') then
              visual_S0_current <= S1;
            else
              visual_S0_current <= S0;
            end if;
 
          when S1 =>
            if (EKLD = '1') then
              E_K<='1';
              visual_S0_current <= S2;
            else
              visual_S0_current <= S1;
            end if;
 
          when S2 =>
            E_K<='0';
            visual_S0_current <= S0;
 
          when others =>
 
            E_K<='0';
            visual_S0_current <= S0;
        end case;
      end if;
    end if;
  end process;
 
end E_K_CTRL;
----------------------------------------------------
--  
--  Library Name :  Idea_vhd_100M
--  Unit    Name :  DE_KEY_CTRL
--  Unit    Type :  State Machine
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_UNSIGNED.all;
entity DE_KEY_CTRL is
  port (
        E_K : in std_logic;
        CLK : in std_logic;
        RST : in std_logic;
        E_MMUL16A1_IN : out std_logic;
        MMUL16A1_INOV : in std_logic;
        DEK_SEL : out std_logic_vector(4 downto 0 );
        KEY_BUSY : out std_logic
        );
 
end DE_KEY_CTRL;
 
 
architecture DE_KEY_CTRL of DE_KEY_CTRL is
 
  signal DEK_SELM : std_logic_vector(4 downto 0 );
 
  type visual_S0_states is (S0, S1, S3);
  signal visual_S0_current : visual_S0_states;
 
 
begin
 
 
 
  -- Synchronous process
  DE_KEY_CTRL_S0:
  process (CLK, RST)
  begin
 
    if (RST = '0') then
      E_MMUL16A1_IN<='0';
      DEK_SELM<="00000";
      KEY_BUSY<='0';
      visual_S0_current <= S0;
    elsif (CLK'event and CLK = '1') then
      if (RST = '0') then
        E_MMUL16A1_IN<='0';
        DEK_SELM<="00000";
        KEY_BUSY<='0';
        visual_S0_current <= S0;
      else
 
        case visual_S0_current is
          when S0 =>
            if (E_K = '1') then