idea_de_top.vhd

IDEA解密运算模块

 
  A1_1(16 downto 0) <= (visual_C16_O);
   process (I1 , S19 , TJ1)
   begin
     case TJ1 is
       when '0' =>
         visual_C16_O <=  I1(16 downto 0);
       when others =>
         visual_C16_O <=  S19(16 downto 0);
     end case;
   end process;
 
 
  S27 <= (visual_C17_O);
   process (OV1 , OV2 , CO_N1N2)
   begin
     case CO_N1N2 is
       when '0' =>
         visual_C17_O <=  OV1;
       when others =>
         visual_C17_O <=  OV2;
     end case;
   end process;
 
 
  S28 <= (visual_C18_O);
   process (OV2 , OV1 , CO_N1N2)
   begin
     case CO_N1N2 is
       when '0' =>
         visual_C18_O <=  OV2;
       when others =>
         visual_C18_O <=  OV1;
     end case;
   end process;
 
 
  S30(16 downto 0) <= "10000000000000001";
 
 
  S161 <= (visual_C92_O);
   process (S158 , S38 , OV1)
   begin
     case OV1 is
       when '0' =>
         visual_C92_O <=  S158;
       when others =>
         visual_C92_O <=  S38;
     end case;
   end process;
 
 
  S158 <= '1';
 
 
  OV_1 <= (visual_C20_O);
   process (OV3 , S161 , OV1 , S35)
   begin
     case S35(1 downto 0) is
       when "00" =>
         visual_C20_O <=  OV3;
       when "01" =>
         visual_C20_O <=  OV3;
       when "10" =>
         visual_C20_O <=  S161;
       when others =>
         visual_C20_O <=  OV1;
     end case;
   end process;
 
 
  S35(1) <= TJ1;
  S35(0) <= TJ3;
 
  S38 <= '0';
 
 
 
    visual_C147_tmp_a <= (S121(16 downto 0));
    visual_C147_tmp_b <= (S26(16 downto 0));
    visual_C147_dif_int <= (unsigned('0' & visual_C147_tmp_a)
       - unsigned('0' & visual_C147_tmp_b));
 
       S180(16 downto 0) <= (visual_C147_dif_int(17 - 1 downto 0));
 
 
  S121(16 downto 0) <= "10000000000000001";
 
 
  Q(15 downto 0) <= (visual_C29_O);
   process (S180 , S26 , OV_20)
   begin
     case OV_20 is
       when '0' =>
         visual_C29_O <=  S180(15 downto 0);
       when others =>
         visual_C29_O <=  S26(15 downto 0);
     end case;
   end process;
 
end MMUL_16A1_IN_2;
----------------------------------------------------
--  
--  Library Name :  Idea_vhd_100M
--  Unit    Name :  MMUL_16A1_IN_CT
--  Unit    Type :  State Machine
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_UNSIGNED.all;
entity MMUL_16A1_IN_CT is
  port (
        CLK : in std_logic;
        RST : in std_logic;
        OV_S : in std_logic;
        CT : out std_logic;
        E : in std_logic;
        E1 : out std_logic;
        OV : out std_logic
        );
 
end MMUL_16A1_IN_CT;
 
 
architecture MMUL_16A1_IN_CT of MMUL_16A1_IN_CT is
 
  type visual_S0_states is (S0, S1, S2, S3);
  signal visual_S0_current : visual_S0_states;
 
 
begin
 
 
 
  -- Synchronous process
  MMUL_16A1_IN_CT_S0:
  process (CLK)
  begin
 
    if (CLK'event and CLK = '1') then
      if (RST = '0') then
        CT<='0';
        E1<='0';
        OV<='0';
        visual_S0_current <= S0;
      elsif (RST = '0') then
        CT<='0';
        E1<='0';
        OV<='0';
        visual_S0_current <= S0;
      else
 
        case visual_S0_current is
          when S0 =>
            if (E = '1') then
              CT<='0';
              E1<='1';
              visual_S0_current <= S1;
            else
              visual_S0_current <= S0;
            end if;
 
          when S1 =>
            CT<='1';
            visual_S0_current <= S2;
 
          when S2 =>
            if (OV_S = '1') then
              OV<='1';
              visual_S0_current <= S3;
            elsif (E = '1') then
              CT<='0';
              E1<='1';
              visual_S0_current <= S1;
            else
              visual_S0_current <= S2;
            end if;
 
          when S3 =>
            CT<='0';
            E1<='0';
            OV<='0';
            visual_S0_current <= S0;
 
          when others =>
 
            CT<='0';
            E1<='0';
            OV<='0';
            visual_S0_current <= S0;
        end case;
      end if;
    end if;
  end process;
 
end MMUL_16A1_IN_CT;
----------------------------------------------------
--  
--  Library Name :  Idea_vhd_100M
--  Unit    Name :  MMUL_16A1_IN_1
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_UNSIGNED.all;
entity MMUL_16A1_IN_1 is
  port (
        A1 : in std_logic_vector(16 downto 0 );
        A1_1 : out std_logic_vector(16 downto 0 );
        A2 : in std_logic_vector(16 downto 0 );
        N1 : in std_logic_vector(16 downto 0 );
        N2 : in std_logic_vector(16 downto 0 );
        N2_1 : out std_logic_vector(16 downto 0 );
        OV1 : in std_logic;
        OV2 : in std_logic;
        OV_1 : out std_logic;
        OV_2 : out std_logic;
        A2_1 : out std_logic_vector(16 downto 0 );
        N1_1 : out std_logic_vector(16 downto 0 )
        );
 
 
end MMUL_16A1_IN_1;
 
 
use work.all;
architecture MMUL_16A1_IN_1 of MMUL_16A1_IN_1 is
 
  signal CO_N1N2 : std_logic;
  signal I1 : std_logic_vector(16 downto 0 );
  signal OV3 : std_logic;
  signal S10 : std_logic_vector(16 downto 0 );
  signal S11 : std_logic_vector(16 downto 0 );
  signal S12 : std_logic_vector(16 downto 0 );
  signal S134 : std_logic;
  signal S158 : std_logic;
  signal S161 : std_logic;
  signal S19 : std_logic_vector(16 downto 0 );
  signal S2 : std_logic_vector(16 downto 0 );
  signal S26 : std_logic_vector(16 downto 0 );
  signal S27 : std_logic;
  signal S28 : std_logic;
  signal S30 : std_logic_vector(16 downto 0 );
  signal S35 : std_logic_vector(1 downto 0 );
  signal S38 : std_logic;
  signal S40 : std_logic_vector(16 downto 0 );
  signal S41 : std_logic_vector(16 downto 0 );
  signal S42 : std_logic_vector(16 downto 0 );
  signal S6 : std_logic_vector(16 downto 0 );
  signal S7 : std_logic_vector(16 downto 0 );
  signal SY : std_logic;
  signal SY1 : std_logic;
  signal TJ1 : std_logic;
  signal TJ3 : std_logic;
  component ADD_17_ST
      port (
            A1 : in std_logic_vector(16 downto 0 );
            A2 : in std_logic_vector(16 downto 0 );
            CO_N1N2 : in std_logic;
            OV : out std_logic;
            OV1 : in std_logic;
            OV2 : in std_logic;
            Q : out std_logic_vector(16 downto 0 )
            );
  end component;
  signal visual_C1_dif_int : std_logic_vector(17 downto 0 );
  signal visual_C1_tmp_a : std_logic_vector(17 - 1 downto 0 );
  signal visual_C1_tmp_b : std_logic_vector(17 - 1 downto 0 );
  constant visual_C1_zero : std_logic_vector(17 - 1 downto 0 ) := (others  =>
                                                  '0');
  signal visual_C13_O : std_logic_vector(17 - 1 downto 0 );
  signal visual_C16_O : std_logic_vector(17 - 1 downto 0 );
  signal visual_C17_O : std_logic;
  signal visual_C18_O : std_logic;
  signal visual_C92_O : std_logic;
  signal visual_C20_O : std_logic;
  signal visual_C142_dif_int : std_logic_vector(17 downto 0 );
  signal visual_C142_tmp_a : std_logic_vector(17 - 1 downto 0 );
  signal visual_C142_tmp_b : std_logic_vector(17 - 1 downto 0 );
  constant visual_C142_zero : std_logic_vector(17 - 1 downto 0 ) := (others  =>
                                                  '0');
  signal visual_C145_O : std_logic_vector(17 - 1 downto 0 );
  signal visual_C12_O : std_logic_vector(17 - 1 downto 0 );
  signal visual_C31_O : std_logic_vector(17 - 1 downto 0 );
  signal visual_C32_O : std_logic_vector(17 - 1 downto 0 );
  signal visual_C24_O : std_logic;
  signal visual_C27_O : std_logic;
 
  -- Start Configuration Specification
  -- ++ for all : ADD_17_ST use entity work.ADD_17_ST(ADD_17_ST);
  -- End Configuration Specification
 
begin
  A2_1 <= S26(16 downto 0);
  N1_1 <= S7(16 downto 0);
 
  C103: ADD_17_ST
    port map (
              A1 => A2(16 downto 0),
              A2 => A1(16 downto 0),
              CO_N1N2 => CO_N1N2,
              OV => OV3,
              OV1 => S27,
              OV2 => S28,
              Q => I1(16 downto 0)
              );
 
 
    visual_C142_tmp_a <= (N1(16 downto 0));
    visual_C142_tmp_b <= (N2(16 downto 0));
    visual_C142_dif_int <= (unsigned('0' & visual_C142_tmp_a)
       - unsigned('0' & visual_C142_tmp_b)) - unsigned(visual_C142_zero & (S134));
 
       S40(16 downto 0) <= (visual_C142_dif_int(17 - 1 downto 0));
 
       CO_N1N2 <= (visual_C142_dif_int(17));
 
  S2(16 downto 0) <= (visual_C145_O);
   process (S42 , S40 , CO_N1N2)
   begin
     case CO_N1N2 is
       when '1' =>
         visual_C145_O <=  S42(16 downto 0);
       when others =>
         visual_C145_O <=  S40(16 downto 0);
     end case;
   end process;
 
 
  S6(16) <= S134;
  S6(15 downto 0) <= N1(16 downto 1);
 
  TJ1 <= not (N1(0));
 
  TJ3 <= not (A1(0));
 
  S134 <= '0';
 
 
  S7(16 downto 0) <= (visual_C12_O);
   process (S2 , S6 , TJ1)
   begin
     case TJ1 is
       when '0' =>
         visual_C12_O <=  S2(16 downto 0);
       when others =>
         visual_C12_O <=  S6(16 downto 0);
     end case;
   end process;
 
 
  N2_1(16 downto 0) <= (visual_C31_O);
   process (N1 , N2 , SY)
   begin
     case SY is
       when '0' =>
         visual_C31_O <=  N1(16 downto 0);
       when others =>
         visual_C31_O <=  N2(16 downto 0);
     end case;
   end process;
 
 
  S26(16 downto 0) <= (visual_C32_O);
   process (A1 , A2 , SY)
   begin
     case SY is
       when '0' =>
         visual_C32_O <=  A1(16 downto 0);
       when others =>
         visual_C32_O <=  A2(16 downto 0);
     end case;
   end process;
 
 
  OV_2 <= (visual_C24_O);
   process (OV1 , OV2 , SY)
   begin
     case SY is
       when '0' =>
         visual_C24_O <=  OV1;
       when others =>
         visual_C24_O <=  OV2;
     end case;
   end process;
 
 
  S41(16 downto 0) <= not (S40(16 downto 0));
 
 
  S42(16 downto 0) <= (unsigned((S41(16 downto 0))) + 1);
 
 
  SY <= (visual_C27_O);
   process (CO_N1N2 , TJ1 , SY1)
   begin
     case SY1 is
       when '0' =>
         visual_C27_O <= not CO_N1N2;
       when others =>
         visual_C27_O <=  TJ1;
     end case;
   end process;
 
 
   SY1 <= ( TJ1) or ( CO_N1N2);
 
 
 
    visual_C1_tmp_a <= (S30(16 downto 0));
    visual_C1_tmp_b <= (A1(16 downto 0));
    visual_C1_dif_int <= (unsigned('0' & visual_C1_tmp_a)
       - unsigned('0' & visual_C1_tmp_b));
 
       S10(16 downto 0) <= (visual_C1_dif_int(17 - 1 downto 0));
 
 
  S11(16) <= S134;
  S11(15 downto 0) <= S10(16 downto 1);
 
  S12(16) <= S134;
  S12(15 downto 0) <= A1(16 downto 1);
 
  S19(16 downto 0) <= (visual_C13_O);
   process (S11 , S12 , TJ3)
   begin
     case TJ3 is
       when '0' =>
         visual_C13_O <=  S11(16 downto 0);
       when others =>
         visual_C13_O <=  S12(16 downto 0);
     end case;
   end process;
 
 
  A1_1(16 downto 0) <= (visual_C16_O);
   process (I1 , S19 , TJ1)
   begin
     case TJ1 is
       when '0' =>
         visual_C16_O <=  I1(16 downto 0);
       when others =>
         visual_C16_O <=  S19(16 downto 0);
     end case;
   end process;
 
 
  S27 <= (visual_C17_O);
   process (OV1 , OV2 , CO_N1N2)
   begin
     case CO_N1N2 is
       when '0' =>
         visual_C17_O <=  OV1;
       when others =>
         visual_C17_O <=  OV2;
     end case;
   end process;
 
 
  S28 <= (visual_C18_O);
   process (OV2 , OV1 , CO_N1N2)
   begin
     case CO_N1N2 is
       when '0' =>
         visual_C18_O <=  OV2;
       when others =>
         visual_C18_O <=  OV1;
     end case;
   end process;
 
 
  S30(16 downto 0) <= "10000000000000001";
 
 
  S161 <= (visual_C92_O);
   process (S158 , S38 , OV1)
   begin
     case OV1 is
       when '0' =>
         visual_C92_O <=  S158;
       when others =>
         visual_C92_O <=  S38;
     end case;
   end process;
 
 
  S158 <= '1';
 
 
  OV_1 <= (visual_C20_O);
   process (OV3 , S161 , OV1 , S35)
   begin
     case S35(1 downto 0) is
       when "00" =>
         visual_C20_O <=  OV3;
       when "01" =>
         visual_C20_O <=  OV3;
       when "10" =>
         visual_C20_O <=  S161;
       when others =>
         visual_C20_O <=  OV1;
     end case;
   end process;