tb_fs.vhd

频率扫描的VHDL完整代码

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-- Company: 
-- Engineer:
--
-- Create Date:   09:32:07 11/29/2011
-- Design Name:   
-- Module Name:   D:/Fre_Sweep/tb_FS.vhd
-- Project Name:  Fre_Sweep
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: FS_Top
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY tb_FS IS
END tb_FS;
 
ARCHITECTURE behavior OF tb_FS IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT FS_Top
    PORT(
         clk : IN  std_logic;
         reset : IN  std_logic;
         IF_center : IN  std_logic_vector(47 downto 0);
         Mod_sel : IN  std_logic_vector(7 downto 0);
         DFRE_max_1 : IN  std_logic_vector(23 downto 0);
         DFRE_max_2 : IN  std_logic_vector(23 downto 0);
         Sweep_step : IN  std_logic_vector(23 downto 0);
         Sweep_N : IN  std_logic_vector(7 downto 0);
         IF_out : OUT  std_logic_vector(47 downto 0);
         Sweep_stop : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';
   signal IF_center : std_logic_vector(47 downto 0) := (others => '0');
   signal Mod_sel : std_logic_vector(7 downto 0) := (others => '0');
   signal DFRE_max_1 : std_logic_vector(23 downto 0) := (others => '0');
   signal DFRE_max_2 : std_logic_vector(23 downto 0) := (others => '0');
   signal Sweep_step : std_logic_vector(23 downto 0) := (others => '0');
   signal Sweep_N : std_logic_vector(7 downto 0) := (others => '0');

 	--Outputs
   signal IF_out : std_logic_vector(47 downto 0);
   signal Sweep_stop : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: FS_Top PORT MAP (
          clk => clk,
          reset => reset,
          IF_center => IF_center,
          Mod_sel => Mod_sel,
          DFRE_max_1 => DFRE_max_1,
          DFRE_max_2 => DFRE_max_2,
          Sweep_step => Sweep_step,
          Sweep_N => Sweep_N,
          IF_out => IF_out,
          Sweep_stop => Sweep_stop
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	
         reset<='0';
         IF_center<=x"002222222222";
         Mod_sel<=x"01";
         DFRE_max_1<=x"000eee";
         DFRE_max_2 <=x"00eeee";
         Sweep_step <=x"00ffff";
         Sweep_N<=x"05";
      wait for clk_period*10;
      -- insert stimulus here 
      wait;
   end process;

END;