fs_top.syr

频率扫描的VHDL完整代码

Release 12.4 - xst M.81d (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.47 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.48 secs
 
--> Reading design: FS_Top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "FS_Top.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "FS_Top"
Output Format                      : NGC
Target Device                      : xc5vsx95t-1-ff1136

---- Source Options
Top Module Name                    : FS_Top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Off
Reduce Control Sets                : Off
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 32
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

---- Other Options
Cores Search Directories           : {"ipcore_dir/tmp/_cg"  }

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/Fre_Sweep/sweep_tri.vhd" in Library work.
Entity <sweep_tri> compiled.
Entity <sweep_tri> (Architecture <Behavioral>) compiled.
Compiling vhdl file "D:/Fre_Sweep/sweep_ech.vhd" in Library work.
Entity <sweep_ech> compiled.
Entity <sweep_ech> (Architecture <Behavioral>) compiled.
Compiling vhdl file "D:/Fre_Sweep/sweep_sine.vhd" in Library work.
Entity <sweep_sine> compiled.
Entity <sweep_sine> (Architecture <Behavioral>) compiled.
Compiling vhdl file "D:/Fre_Sweep/FS_Top.vhd" in Library work.
Entity <FS_Top> compiled.
ERROR:HDLParsers:526 - "D:/Fre_Sweep/FS_Top.vhd" Line 59. Non array type std_logic can not have a index constraint.
ERROR:HDLParsers:526 - "D:/Fre_Sweep/FS_Top.vhd" Line 67. Non array type std_logic can not have a index constraint.
ERROR:HDLParsers:526 - "D:/Fre_Sweep/FS_Top.vhd" Line 74. Non array type std_logic can not have a index constraint.
ERROR:HDLParsers:850 - "D:/Fre_Sweep/FS_Top.vhd" Line 89. Formal port acc_T does not exist in Component 'sweep_tri'.
ERROR:HDLParsers:850 - "D:/Fre_Sweep/FS_Top.vhd" Line 97. Formal port acc_T does not exist in Component 'sweep_ech'.
ERROR:HDLParsers:850 - "D:/Fre_Sweep/FS_Top.vhd" Line 104. Formal port acc_T does not exist in Component 'sweep_sine'.
ERROR:HDLParsers:3313 - "D:/Fre_Sweep/FS_Top.vhd" Line 111. Undefined symbol 'mode_sel'.  Should it be: mod_sel?
ERROR:HDLParsers:1209 - "D:/Fre_Sweep/FS_Top.vhd" Line 111. mode_sel: Undefined symbol (last report in this block)
ERROR:HDLParsers:3384 - "D:/Fre_Sweep/FS_Top.vhd" Line 119. Size mismatch.  String literal "0000000000000000" is of size 16 but is expected to be of size 24.
ERROR:HDLParsers:808 - "D:/Fre_Sweep/FS_Top.vhd" Line 128. + can not have such operands in this context.
ERROR:HDLParsers:3384 - "D:/Fre_Sweep/FS_Top.vhd" Line 142. Size mismatch.  String literal "0000000000000000" is of size 16 but is expected to be of size 48.
ERROR:HDLParsers:808 - "D:/Fre_Sweep/FS_Top.vhd" Line 144. + can not have such operands in this context.
--> 

Total memory usage is 170928 kilobytes

Number of errors   :   12 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)