sweep_dds.v

频率扫描的VHDL完整代码

  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut2_DOB<12>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut2_DOB<11>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut2_DOB<10>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut2_DOB<9>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut2_DOB<8>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut2_DOB<7>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut2_DOB<6>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut2_DOPB<3>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut2_DOPB<2>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut2_DOPB<1>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut2_DOPB<0>_UNCONNECTED ;
  wire [31 : 0] pinc_in_2;
  wire [15 : 0] sine_3;
  wire [1 : 0] \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.pipe_4 ;
  wire [8 : 0] \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ls/opt_has_pipe.first_q ;
  wire [8 : 0] \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ls/opt_has_pipe.first_q ;
  wire [7 : 0] \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms/opt_has_pipe.first_q ;
  wire [6 : 0] \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.asyn_sin_ms1 ;
  wire [7 : 0] \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms/opt_has_pipe.first_q ;
  wire [7 : 0] \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.asyn_cos_ms1 ;
  wire [0 : 0] \BU2/U0/I_SINCOS.i_rom/Madd_i_rtl.i_quarter_table.i_piped_map.asyn_sin_ms2_lut ;
  wire [7 : 1] \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.asyn_sin_ms2 ;
  wire [7 : 0] \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q ;
  wire [0 : 0] \BU2/U0/I_SINCOS.i_rom/Madd_i_rtl.i_quarter_table.i_piped_map.asyn_cos_ms2_lut ;
  wire [7 : 1] \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.asyn_cos_ms2 ;
  wire [7 : 0] \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q ;
  wire [14 : 0] \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/opt_has_pipe.first_q ;
  wire [14 : 0] \BU2/U0/I_SINCOS.i_rom/asyn_sin_RAM_op ;
  wire [14 : 0] \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/opt_has_pipe.first_q ;
  wire [14 : 0] \BU2/U0/I_SINCOS.i_rom/asyn_cos_RAM_op ;
  wire [1 : 0] \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q ;
  wire [11 : 0] \BU2/U0/I_SINCOS.i_rom/mod_sin_addr ;
  wire [11 : 0] \BU2/U0/I_SINCOS.i_rom/asyn_mod_sin_addr ;
  wire [7 : 0] \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.asyn_sin_ls1 ;
  wire [7 : 1] \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.asyn_sin_ls1_pre ;
  wire [7 : 0] \BU2/U0/I_SINCOS.i_rom/Madd_i_rtl.i_quarter_table.i_piped_map.asyn_sin_ls1_cy ;
  wire [0 : 0] \BU2/U0/I_SINCOS.i_rom/Madd_i_rtl.i_quarter_table.i_piped_map.asyn_cos_ls1_lut ;
  wire [8 : 1] \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.asyn_cos_ls1 ;
  wire [7 : 0] \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.asyn_cos_ls1_pre ;
  wire [8 : 0] \BU2/U0/I_SINCOS.i_rom/Madd_i_rtl.i_quarter_table.i_piped_map.asyn_cos_ls1_cy ;
  wire [9 : 0] \BU2/U0/I_PHASEGEN.i_dither.dither_i ;
  wire [32 : 0] \BU2/U0/I_PHASEGEN.i_fabric.i_dither_pipe/opt_has_pipe.first_q ;
  wire [32 : 0] \BU2/U0/acc_phase_shaped_pre ;
  wire [32 : 0] \BU2/U0/I_PHASEGEN.i_accum/i_fabric.i_common.i_phase_acc/opt_has_pipe.first_q ;
  wire [32 : 0] \BU2/U0/I_PHASEGEN.i_accum/i_fabric.acc_phase_b ;
  wire [31 : 0] \BU2/U0/I_PHASEGEN.i_accum/i_fabric.i_one_channel.i_accum/Madd_i_top_seg.temp_Madd_lut ;
  wire [30 : 0] \BU2/U0/I_PHASEGEN.i_accum/i_fabric.i_one_channel.i_accum/Madd_i_top_seg.temp_Madd_cy ;
  wire [31 : 0] \BU2/U0/I_PHASEGEN.i_fabric.i_dither_add.i_dither_add/Madd_i_top_seg.temp_Madd_lut ;
  wire [30 : 0] \BU2/U0/I_PHASEGEN.i_fabric.i_dither_add.i_dither_add/Madd_i_top_seg.temp_Madd_cy ;
  wire [25 : 11] \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr ;
  assign
    sine[15] = sine_3[15],
    sine[14] = sine_3[14],
    sine[13] = sine_3[13],
    sine[12] = sine_3[12],
    sine[11] = sine_3[11],
    sine[10] = sine_3[10],
    sine[9] = sine_3[9],
    sine[8] = sine_3[8],
    sine[7] = sine_3[7],
    sine[6] = sine_3[6],
    sine[5] = sine_3[5],
    sine[4] = sine_3[4],
    sine[3] = sine_3[3],
    sine[2] = sine_3[2],
    sine[1] = sine_3[1],
    sine[0] = sine_3[0],
    pinc_in_2[31] = pinc_in[31],
    pinc_in_2[30] = pinc_in[30],
    pinc_in_2[29] = pinc_in[29],
    pinc_in_2[28] = pinc_in[28],
    pinc_in_2[27] = pinc_in[27],
    pinc_in_2[26] = pinc_in[26],
    pinc_in_2[25] = pinc_in[25],
    pinc_in_2[24] = pinc_in[24],
    pinc_in_2[23] = pinc_in[23],
    pinc_in_2[22] = pinc_in[22],
    pinc_in_2[21] = pinc_in[21],
    pinc_in_2[20] = pinc_in[20],
    pinc_in_2[19] = pinc_in[19],
    pinc_in_2[18] = pinc_in[18],
    pinc_in_2[17] = pinc_in[17],
    pinc_in_2[16] = pinc_in[16],
    pinc_in_2[15] = pinc_in[15],
    pinc_in_2[14] = pinc_in[14],
    pinc_in_2[13] = pinc_in[13],
    pinc_in_2[12] = pinc_in[12],
    pinc_in_2[11] = pinc_in[11],
    pinc_in_2[10] = pinc_in[10],
    pinc_in_2[9] = pinc_in[9],
    pinc_in_2[8] = pinc_in[8],
    pinc_in_2[7] = pinc_in[7],
    pinc_in_2[6] = pinc_in[6],
    pinc_in_2[5] = pinc_in[5],
    pinc_in_2[4] = pinc_in[4],
    pinc_in_2[3] = pinc_in[3],
    pinc_in_2[2] = pinc_in[2],
    pinc_in_2[1] = pinc_in[1],
    pinc_in_2[0] = pinc_in[0];
  VCC   VCC_0 (
    .P(NLW_VCC_P_UNCONNECTED)
  );
  GND   GND_1 (
    .G(NLW_GND_G_UNCONNECTED)
  );
  FDE #(
    .INIT ( 1'b0 ))
  \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.pipe_4_0  (
    .C(clk),
    .CE(ce),
    .D(\BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/Mshreg_opt_has_pipe.pipe_4_0_790 ),
    .Q(\BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.pipe_4 [0])
  );
  SRLC16E #(
    .INIT ( 16'h0000 ))
  \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/Mshreg_opt_has_pipe.pipe_4_0  (
    .A0(\BU2/N1 ),
    .A1(\BU2/N0 ),
    .A2(\BU2/N0 ),
    .A3(\BU2/N0 ),
    .CE(ce),
    .CLK(clk),
    .D(\BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q [0]),
    .Q(\BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/Mshreg_opt_has_pipe.pipe_4_0_790 ),
    .Q15(\NLW_BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/Mshreg_opt_has_pipe.pipe_4_0_Q15_UNCONNECTED )
  );
  FDE #(
    .INIT ( 1'b0 ))
  \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.pipe_4_1  (
    .C(clk),
    .CE(ce),
    .D(\BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/Mshreg_opt_has_pipe.pipe_4_1_789 ),
    .Q(\BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.pipe_4 [1])
  );
  SRLC16E #(
    .INIT ( 16'h0000 ))
  \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/Mshreg_opt_has_pipe.pipe_4_1  (
    .A0(\BU2/N1 ),
    .A1(\BU2/N0 ),
    .A2(\BU2/N0 ),
    .A3(\BU2/N0 ),
    .CE(ce),
    .CLK(clk),
    .D(\BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q [1]),
    .Q(\BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/Mshreg_opt_has_pipe.pipe_4_1_789 ),
    .Q15(\NLW_BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/Mshreg_opt_has_pipe.pipe_4_1_Q15_UNCONNECTED )
  );
  RAMB36_EXP #(
    .INIT_7E ( 256'hFBFBFBFBFBFBFAFAFAFAFAF9F9F9F9F9F8F8F8F8F7F7F7F7F6F6F6F5F5F5F5F4 ),
    .INIT_7F ( 256'hFEFEFEFEFEFEFEFEFEFEFEFEFEFEFDFDFDFDFDFDFDFDFDFDFDFCFCFCFCFCFCFC ),
    .INITP_00 ( 256'h001FFFFF00000FFFFF800007FFFF800003FFFFC00001FFFFE00001FFFFF00000 ),
    .INITP_01 ( 256'h00000FFFFF800003FFFFC00001FFFFF00000FFFFF800007FFFFC00003FFFFE00 ),
    .INITP_02 ( 256'hE000007FFFFC00001FFFFF000007FFFFC00001FFFFF000007FFFFC00001FFFFE ),
    .INITP_03 ( 256'h000003FFFFF000007FFFFE000007FFFFE00000FFFFFC00001FFFFF800003FFFF ),
    .INITP_04 ( 256'h00FFFFFE000003FFFFF000001FFFFFC00000FFFFFE000007FFFFE000003FFFFF ),
    .INITP_05 ( 256'hE000001FFFFFE000001FFFFFE000001FFFFFE000001FFFFFC000007FFFFF8000 ),
    .INITP_06 ( 256'hF8000001FFFFFF8000001FFFFFF8000003FFFFFE0000007FFFFF8000003FFFFF ),
    .INITP_07 ( 256'h0001FFFFFFE0000001FFFFFFE0000001FFFFFFC0000007FFFFFF0000001FFFFF ),
    .INITP_08 ( 256'h00000003FFFFFFF80000000FFFFFFFE00000007FFFFFFE00000007FFFFFFC000 ),
    .INITP_09 ( 256'h0001FFFFFFFFE000000001FFFFFFFF800000001FFFFFFFF800000003FFFFFFFC ),
    .INITP_0A ( 256'h0000000003FFFFFFFFFE0000000001FFFFFFFFFE0000000007FFFFFFFFE00000 ),
    .INITP_0B ( 256'h0007FFFFFFFFFFFF8000000000003FFFFFFFFFFF800000000001FFFFFFFFFFE0 ),
    .INITP_0C ( 256'h000000007FFFFFFFFFFFFFFFC000000000000003FFFFFFFFFFFFFE0000000000 ),
    .INITP_0D ( 256'hFFFFFFFFFFFFF80000000000000000000007FFFFFFFFFFFFFFFFFFE000000000 ),
    .SRVAL_A ( 36'h000000000 ),
    .SRVAL_B ( 36'h000000000 ),
    .INIT_00 ( 256'h8C7F73665A4D4034271B0E02F5E8DCCFC3B6AA9D9184776B5E5245392C1F1306 ),
    .INIT_01 ( 256'h1E1105F8ECDFD2C6B9ADA094877B6E6155483C2F231609FDF0E4D7CBBEB2A598 ),
    .INIT_02 ( 256'hB0A3978A7E7164584B3F3226190C00F3E7DACEC1B5A89B8F8276695D5044372A ),
    .INIT_03 ( 256'h4135281C0F03F6EADDD1C4B7AB9E9285796C6053463A2D211408FBEFE2D5C9BC ),
    .INIT_04 ( 256'hD3C6BAADA194887B6F6256493C3023170AFEF1E5D8CCBFB2A6998D8074675B4E ),
    .INIT_05 ( 256'h64584B3F3225190C00F3E7DACEC1B5A89C8F8376695D5044372B1E1205F9ECE0 ),
    .INIT_06 ( 256'hF5E8DCCFC3B6AA9D9184786B5F5246392D201407FBEEE1D5C8BCAFA3968A7D71 ),
    .INIT_07 ( 256'h85796C6053473A2E211508FCEFE3D6CABDB1A4988B7F7266594D4034271B0E01 ),
    .INIT_08 ( 256'h1509FCF0E3D7CABEB1A5988C7F73665A4D4134281B0F02F6E9DDD0C4B7AB9E92 ),