sweep_dds.v

频率扫描的VHDL完整代码

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: M.81d
//  \   \         Application: netgen
//  /   /         Filename: sweep_dds.v
// /___/   /\     Timestamp: Tue Nov 29 15:06:50 2011
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -intstyle ise -w -sim -ofmt verilog ./tmp/_cg\sweep_dds.ngc ./tmp/_cg\sweep_dds.v 
// Device	: 5vsx95tff1136-2
// Input file	: ./tmp/_cg/sweep_dds.ngc
// Output file	: ./tmp/_cg/sweep_dds.v
// # of Modules	: 1
// Design Name	: sweep_dds
// Xilinx        : D:\Xilinx\12.4\ISE_DS\ISE\
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module sweep_dds (
  ce, clk, sine, pinc_in
)/* synthesis syn_black_box syn_noprune=1 */;
  input ce;
  input clk;
  output [15 : 0] sine;
  input [31 : 0] pinc_in;
  
  // synthesis translate_off
  
  wire \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/Mshreg_opt_has_pipe.pipe_4_0_790 ;
  wire \BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/Mshreg_opt_has_pipe.pipe_4_1_789 ;
  wire \BU2/U0/I_SINCOS.i_rom/N20 ;
  wire \BU2/U0/I_SINCOS.i_rom/N21 ;
  wire \BU2/U0/I_SINCOS.i_rom/Madd_i_rtl.i_quarter_table.i_piped_map.asyn_sin_ls1_cy<0>_rt_616 ;
  wire \BU2/N1 ;
  wire \BU2/N0 ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[25]_lfsr[15]_MUX_37_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[24]_lfsr[14]_MUX_38_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[23]_lfsr[13]_MUX_39_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[22]_lfsr[12]_MUX_40_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[21]_lfsr[11]_MUX_41_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[20]_lfsr[10]_MUX_42_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[19]_lfsr[9]_MUX_43_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[18]_lfsr[8]_MUX_44_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[17]_lfsr[7]_MUX_45_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[16]_lfsr[6]_MUX_46_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[15]_lfsr[5]_MUX_47_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[14]_lfsr[4]_MUX_48_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[13]_lfsr[3]_MUX_49_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[12]_lfsr[2]_MUX_50_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[11]_lfsr[1]_MUX_51_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[10]_lfsr[25]_MUX_52_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[9]_lfsr[24]_MUX_53_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[8]_lfsr[23]_MUX_54_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[7]_lfsr[22]_MUX_55_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[6]_lfsr[21]_MUX_56_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[5]_lfsr[20]_MUX_57_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[4]_lfsr[19]_MUX_58_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[3]_lfsr[18]_MUX_59_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[2]_lfsr[17]_MUX_60_o ;
  wire \BU2/U0/I_PHASEGEN.i_dither.i_dither/lfsr[1]_lfsr[16]_MUX_61_o ;
  wire NLW_VCC_P_UNCONNECTED;
  wire NLW_GND_G_UNCONNECTED;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/Mshreg_opt_has_pipe.pipe_4_0_Q15_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/Mshreg_opt_has_pipe.pipe_4_1_Q15_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_CASCADEINLATA_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_CASCADEINLATB_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_CASCADEINREGA_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_CASCADEINREGB_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_CASCADEOUTLATA_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_CASCADEOUTLATB_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_CASCADEOUTREGA_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_CASCADEOUTREGB_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<31>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<30>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<29>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<28>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<27>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<26>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<25>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<24>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<23>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<22>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<21>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<20>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<19>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<18>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<17>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<16>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<15>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<14>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<13>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<12>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<11>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<10>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<9>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIA<8>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIPA<3>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIPA<2>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIPA<1>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<31>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<30>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<29>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<28>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<27>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<26>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<25>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<24>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<23>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<22>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<21>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<20>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<19>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<18>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<17>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<16>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<15>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<14>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<13>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<12>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<11>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<10>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<9>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<8>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<7>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<6>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<5>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<4>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<3>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<2>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<1>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIB<0>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIPB<3>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIPB<2>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIPB<1>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DIPB<0>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_ADDRAL<2>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_ADDRAL<1>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_ADDRAL<0>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_ADDRAU<2>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_ADDRAU<1>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_ADDRAU<0>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_ADDRBL<2>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_ADDRBL<1>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_ADDRBL<0>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_ADDRBU<2>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_ADDRBU<1>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_ADDRBU<0>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DOA<31>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DOA<30>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DOA<29>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DOA<28>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DOA<27>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DOA<26>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DOA<25>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DOA<24>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DOA<23>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DOA<22>_UNCONNECTED ;
  wire \NLW_BU2/U0/I_SINCOS.i_rom/Mram_sin_cos_lut1_DOA<21>_UNCONNECTED ;