mul_sweep.vhd

频率扫描的VHDL完整代码

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-- You must compile the wrapper file mul_sweep.vhd when simulating
-- the core, mul_sweep. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY mul_sweep IS
	port (
	clk: in std_logic;
	a: in std_logic_vector(31 downto 0);
	b: in std_logic_vector(15 downto 0);
	p: out std_logic_vector(47 downto 0));
END mul_sweep;

ARCHITECTURE mul_sweep_a OF mul_sweep IS
-- synthesis translate_off
component wrapped_mul_sweep
	port (
	clk: in std_logic;
	a: in std_logic_vector(31 downto 0);
	b: in std_logic_vector(15 downto 0);
	p: out std_logic_vector(47 downto 0));
end component;

-- Configuration specification 
	for all : wrapped_mul_sweep use entity XilinxCoreLib.mult_gen_v11_2(behavioral)
		generic map(
			c_a_width => 32,
			c_b_type => 0,
			c_ce_overrides_sclr => 0,
			c_has_sclr => 0,
			c_round_pt => 0,
			c_model_type => 0,
			c_out_high => 47,
			c_verbosity => 0,
			c_mult_type => 0,
			c_ccm_imp => 0,
			c_latency => 3,
			c_has_ce => 0,
			c_has_zero_detect => 0,
			c_round_output => 0,
			c_optimize_goal => 1,
			c_xdevicefamily => "virtex5",
			c_a_type => 1,
			c_out_low => 0,
			c_b_width => 16,
			c_b_value => "10000001");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_mul_sweep
		port map (
			clk => clk,
			a => a,
			b => b,
			p => p);
-- synthesis translate_on

END mul_sweep_a;