📄 coregen.cgp
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SET designentry = VHDL
SET BusFormat = BusFormatAngleBracketNotRipped
SET devicefamily = virtex5
SET device = xc5vsx95t
SET package = ff1136
SET speedgrade = -1
SET FlowVendor = Foundation_ISE
SET VerilogSim = True
SET VHDLSim = True
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