coregen.cgp

频率扫描的VHDL完整代码

SET designentry = VHDL
SET BusFormat = BusFormatAngleBracketNotRipped
SET devicefamily = virtex5
SET device = xc5vsx95t
SET package = ff1136
SET speedgrade = -1
SET FlowVendor = Foundation_ISE
SET VerilogSim = True
SET VHDLSim = True