mul_sweep.xco

频率扫描的VHDL完整代码

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SET designentry = VHDL
SET BusFormat = BusFormatAngleBracketNotRipped
SET devicefamily = virtex5
SET device = xc5vsx95t
SET package = ff1136
SET speedgrade = -1
SET FlowVendor = Foundation_ISE
SET VerilogSim = True
SET VHDLSim = True
SELECT Multiplier family Xilinx,_Inc. 11.2
CSET ccmimp=Distributed_Memory
CSET clockenable=false
CSET component_name=mul_sweep
CSET constvalue=129
CSET internaluser=0
CSET multiplier_construction=Use_LUTs
CSET multtype=Parallel_Multiplier
CSET optgoal=Speed
CSET outputwidthhigh=47
CSET outputwidthlow=0
CSET pipestages=3
CSET portatype=Unsigned
CSET portawidth=24
CSET portbtype=Signed
CSET portbwidth=24
CSET roundpoint=0
CSET sclrcepriority=SCLR_Overrides_CE
CSET syncclear=false
CSET use_custom_output_width=false
CSET userounding=false
CSET zerodetect=false
GENERATE