modelsim.ini

频率扫描的VHDL完整代码

; AssertFile = assert.log

; Run simulator in assertion debug mode. Default is off.
; AssertionDebug = 1

; Turn on/off PSL/SVA concurrent assertion pass enable. 
; For SVA, Default is on when the assertion has a pass action block, or
; the vsim -assertdebug option is used and the vopt "+acc=a" flag is active.
; For PSL, Default is on only when vsim switch "-assertdebug" is used
; and the vopt "+acc=a" flag is active.
; AssertionPassEnable = 0 

; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on.
; AssertionFailEnable = 0

; Set PSL/SVA concurrent assertion pass limit. Default is -1.
; Any positive integer, -1 for infinity.
; AssertionPassLimit = 1

; Set PSL/SVA concurrent assertion fail limit. Default is -1.
; Any positive integer, -1 for infinity.
; AssertionFailLimit = 1

; Turn on/off PSL concurrent assertion pass log. Default is off.
; The flag does not affect SVA
; AssertionPassLog = 1

; Turn on/off PSL concurrent assertion fail log. Default is on.
; The flag does not affect SVA
; AssertionFailLog = 0

; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode.  Default is on.
; AssertionFailLocalVarLog = 0

; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
; 0 = Continue  1 = Break  2 = Exit
; AssertionFailAction = 1

; Enable the active thread monitor in the waveform display when assertion debug is enabled.
; AssertionActiveThreadMonitor = 1

; Control how many waveform rows will be used for displaying the active threads.  Default is 5.
; AssertionActiveThreadMonitorLimit = 5


; As per strict 1850-2005 PSL LRM, an always property can either pass
; or fail. However, by default, Questa reports multiple passes and
; multiple fails on top always/never property (always/never operator
; is the top operator under Verification Directive). The reason
; being that Questa reports passes and fails on per attempt of the
; top always/never property. Use the following flag to instruct
; Questa to strictly follow LRM. With this flag, all assert/never
; directives will start an attempt once at start of simulation.
; The attempt can either fail, match or match vacuously.
; For e.g. if always is the top operator under assert, the always will
; keep on checking the property at every clock. If the property under
; always fails, the directive will be considered failed and no more 
; checking will be done for that directive. A top always property,
; if it does not fail, will show a pass at end of simulation.
; The default value is '0' (i.e. zero is off). For example:
; PslOneAttempt = 1

; Specify the number of clock ticks to represent infinite clock ticks.
; This affects eventually!, until! and until_!. If at End of Simulation
; (EOS) an active strong-property has not clocked this number of
; clock ticks then neither pass or fail (vacuous match) is returned
; else respective fail/pass is returned. The default value is '0' (zero)
; which effectively does not check for clock tick condition. For example:
; PslInfinityThreshold = 5000

; Control how many thread start times will be preserved for ATV viewing for a given assertion
; instance.  Default is -1 (ALL).
; ATVStartTimeKeepCount = -1

; Turn on/off code coverage
; CodeCoverage = 0

; Count all code coverage condition and expression truth table rows that match.
; CoverCountAll = 1

; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
; is to include them.
; ToggleNoIntegers = 1

; Set the maximum number of values that are collected for toggle coverage of
; VHDL integers. Default is 100;
; ToggleMaxIntValues = 100

; Set the maximum number of values that are collected for toggle coverage of
; Verilog real. Default is 100;
; ToggleMaxRealValues = 100

; Turn on automatic inclusion of Verilog integers in toggle coverage, except
; for enumeration types. Default is to include them.
; ToggleVlogIntegers = 0

; Turn on automatic inclusion of Verilog real type in toggle coverage, except
; for shortreal types. Default is to not include them.
; ToggleVlogReal = 1

; Turn on automatic inclusion of Verilog fixed-size unpacked arrays in toggle coverage.
; Default is to not include them.
; ToggleFixedSizeArray = 1

; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays that
; are included for toggle coverage. This leads to a longer simulation time with bigger
; arrays covered with toggle coverage. Default is 1024.
; ToggleMaxFixedSizeArray = 1024

; Treat packed vectors and structures as reg-vectors in toggle coverage. Default is 0.
; TogglePackedAsVec = 0

; Treat Verilog enumerated types as reg-vectors in toggle coverage. Default is 0.
; ToggleVlogEnumBits = 0

; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
; For unlimited width, set to 0.
; ToggleWidthLimit = 128

; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
; reached this count, further activity on the bit is ignored. Default is 1.
; For unlimited counts, set to 0.
; ToggleCountLimit = 1

; Turn on/off all PSL/SVA cover directive enables.  Default is on.
; CoverEnable = 0

; Turn on/off PSL/SVA cover log.  Default is off "0".
; CoverLog = 1

; Set "at_least" value for all PSL/SVA cover directives.  Default is 1.
; CoverAtLeast = 2

; Set "limit" value for all PSL/SVA cover directives.  Default is -1.
; Any positive integer, -1 for infinity.
; CoverLimit = 1

; Specify the coverage database filename.
; Default is "" (i.e. database is NOT automatically saved on close). 
; UCDBFilename = vsim.ucdb

; Specify the maximum limit for the number of Cross (bin) products reported
; in XML and UCDB report against a Cross. A warning is issued if the limit
; is crossed.
; MaxReportRhsSVCrossProducts = 1000

; Specify the override for the "auto_bin_max" option for the Covergroups.
; If not specified then value from Covergroup "option" is used.
; SVCoverpointAutoBinMax = 64

; Specify the override for the value of "cross_num_print_missing"
; option for the Cross in Covergroups. If not specified then value
; specified in the "option.cross_num_print_missing" is used. This
; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
; value specified by user in source file and any SVCrossNumPrintMissingDefault
; specified in modelsim.ini.
; SVCrossNumPrintMissing = 0

; Specify whether to use the value of "cross_num_print_missing"
; option in report and GUI for the Cross in Covergroups. If not specified then 
; cross_num_print_missing is ignored for creating reports and displaying 
; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
; UseSVCrossNumPrintMissing = 0

; Specify the override for the value of "strobe" option for the
; Covergroup Type. If not specified then value in "type_option.strobe"
; will be used. This is runtime option which forces "strobe" to
; user specified value and supersedes user specified values in the
; SystemVerilog Code. NOTE: This also overrides the compile time
; default value override specified using "SVCovergroupStrobeDefault"
; SVCovergroupStrobe = 0

; Override for explicit assignments in source code to "option.goal" of
; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
; default value of "option.goal" (defined to be 100 in the SystemVerilog
; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
; SVCovergroupGoal = 100

; Override for explicit assignments in source code to "type_option.goal" of
; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
; SVCovergroupTypeGoal = 100

; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
; builtin functions, and report. This setting changes the default values of
; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
; behavior if explicit assignments are not made on option.get_inst_coverage and
; type_option.merge_instances by the user. There are two vsim command line
; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
; The default value of this variable is 1
; SVCovergroup63Compatibility = 1

; Enable or disable generation of more detailed information about the sampling
; of covergroup, cross, and coverpoints. It provides the details of the number
; of times the covergroup instance and type were sampled, as well as details
; about why covergroup, cross and coverpoint were not covered. A non-zero value
; is to enable this feature. 0 is to disable this feature. Default is 0
; SVCovergroupSampleInfo = 0

; Specify the maximum number of Coverpoint bins in whole design for
; all Covergroups.
; MaxSVCoverpointBinsDesign = 2147483648 

; Specify maximum number of Coverpoint bins in any instance of a Covergroup
; MaxSVCoverpointBinsInst = 2147483648

; Specify the maximum number of Cross bins in whole design for
; all Covergroups.
; MaxSVCrossBinsDesign = 2147483648 

; Specify maximum number of Cross bins in any instance of a Covergroup
; MaxSVCrossBinsInst = 2147483648

; Set weight for all PSL/SVA cover directives.  Default is 1.
; CoverWeight = 2

; Check vsim plusargs.  Default is 0 (off).
; 0 = Don't check plusargs
; 1 = Warning on unrecognized plusarg
; 2 = Error and exit on unrecognized plusarg
; CheckPlusargs = 1

; Load the specified shared objects with the RTLD_GLOBAL flag.
; This gives global visibility to all symbols in the shared objects,
; meaning that subsequently loaded shared objects can bind to symbols
; in the global shared objects.  The list of shared objects should
; be whitespace delimited.  This option is not supported on the
; Windows or AIX platforms.
; GlobalSharedObjectList = example1.so example2.so example3.so

; Run the 0in tools from within the simulator. 
; Default is off.
; ZeroIn = 1

; Set the options to be passed to the 0in runtime tool.
; Default value set to "".
; ZeroInOptions = ""

; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog).
; Sv_Seed = 0

; Specify if the solver should attempt to ignore overflow/underflow semantics
; for arithmetic constraints (multiply, addition, subtraction) in order to
; improve performance. The "solveignoreoverflow" attribute can be specified on
; a per-call basis to randomize() to override this setting.
; The default value is 0 (overflow/underflow is not ignored). Set to 1 to
; ignore overflow/underflow.
; SolveIgnoreOverflow = 0

; Maximum size of dynamic arrays that are resized during randomize().
; The default is 1000. A value of 0 indicates no limit.
; SolveArrayResizeMax = 1000

; Error message severity when randomize() failure is detected (SystemVerilog).
; The default is 0 (no error).
; 0 = No error  1 = Warning  2 = Error  3 = Failure  4 = Fatal
; SolveFailSeverity = 0

; Enable/disable debug information for randomize() failures (SystemVerilog).
; The default is 0 (disabled). Set to 1 to enable.
; SolveFailDebug = 0

; Maximum size of the solution graph that may be generated during randomize().
; This value can be used to force randomize() to abort if the memory
; requirements of the constraint scenario exceeds the specified limit. This
; value is specified in 1000s of nodes.
; The default is 10000. A value of 0 indicates no limit.
; SolveGraphMaxSize = 10000

; Maximum number of evaluations that may be performed on the solution graph
; generated during randomize(). This value can be used to force randomize() to
; abort if