modelsim.ini

频率扫描的VHDL完整代码

;
; A space separated list of resource libraries that contain precompiled
; packages.  The behavior is identical to using the "-L" switch.
; 
; LibrarySearchPath = <path/lib> [<path/lib> ...]
LibrarySearchPath = mtiAvm mtiOvm mtiUPF

; The behavior is identical to the "-mixedansiports" switch.  Default is off.
; MixedAnsiPorts = 1

; Enable SystemVerilog 3.1a $typeof() function. Default is off.
; EnableTypeOf = 1

; Only allow lower case pragmas. Default is disabled.
; AcceptLowerCasePragmaOnly = 1

; Set the maximum depth permitted for a recursive include file nesting.
; IncludeRecursionDepthMax = 5

; Turn off detection of FSMs having single bit current state variable.
; FsmSingle = 0

; Turn off reset state transitions in FSM.
; FsmResetTrans = 0

; Turn off detections of FSMs having x-assignment.
; FsmXAssign = 0

; List of file suffixes which will be read as SystemVerilog.  White space
; in extensions can be specified with a back-slash: "\ ".  Back-slashes
; can be specified with two consecutive back-slashes: "\\";
; SVFileExtensions = sv svp svh

; This setting is the same as the vlog -sv command line switch.
; Enables SystemVerilog features and keywords when true (1).
; When false (0), the rules of IEEE Std 1364-2001 are followed and 
; SystemVerilog keywords are ignored. 
; Svlog = 0

; Prints attribute placed upon SV packages during package import
; when true (1).  The attribute will be ignored when this
; entry is false (0). The attribute name is "package_load_message".
; The value of this attribute is a string literal.
; Default is true (1).
; PrintSVPackageLoadingAttribute = 1

; Do not show immediate assertions with constant expressions in 
; GUI/reports/UCDB etc. By default immediate assertions with constant 
; expressions are shown in GUI/reports/UCDB etc. This does not affect 
; evaluation of immediate assertions.
; ShowConstantImmediateAsserts = 0

[sccom]
; Enable use of SCV include files and library.  Default is off.
; UseScv = 1

; Add C++ compiler options to the sccom command line by using this variable.
; CppOptions = -g

; Use custom C++ compiler located at this path rather than the default path.
; The path should point directly at a compiler executable.
; CppPath = /usr/bin/g++

; Enable verbose messages from sccom.  Default is off.
; SccomVerbose = 1

; sccom logfile.  Default is no logfile.
; SccomLogfile = sccom.log

; Enable use of SC_MS include files and library.  Default is off.
; UseScMs = 1

[vopt]
; Turn on code coverage in vopt.  Default is off. 
; Coverage = sbceft

; Control compiler optimizations that are allowed when
; code coverage is on.  Refer to the comment for this in the [vlog] area. 
; CoverOpt = 3

; Increase or decrease the maximum number of rows allowed in a UDP table
; implementing a vopt condition coverage or expression coverage expression.
; More rows leads to a longer compile time, but more expressions covered.
; CoverMaxUDPRows = 192

; Increase or decrease the maximum number of input patterns that are present
; in FEC table. This leads to a longer compile time with more expressions
; covered with FEC metric.
; CoverMaxFECRows = 192

; Do not show immediate assertions with constant expressions in 
; GUI/reports/UCDB etc. By default immediate assertions with constant 
; expressions are shown in GUI/reports/UCDB etc. This does not affect 
; evaluation of immediate assertions.
; ShowConstantImmediateAsserts = 0

; Set the maximum number of iterations permitted for a generate loop.
; Restricting this permits the implementation to recognize infinite
; generate loops.
; GenerateLoopIterationMax = 100000

; Set the maximum depth permitted for a recursive generate instantiation.
; Restricting this permits the implementation to recognize infinite
; recursions.
; GenerateRecursionDepthMax = 200


[vsim]
; vopt flow
; Set to turn on automatic optimization of a design.
; Default is on
VoptFlow = 1

; vopt automatic SDF
; If automatic design optimization is on, enables automatic compilation
; of SDF files.
; Default is on, uncomment to turn off.
; VoptAutoSDFCompile = 0

; Automatic SDF compilation
; Disables automatic compilation of SDF files in flows that support it.
; Default is on, uncomment to turn off.
; NoAutoSDFCompile = 1

; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
Resolution = ps

; Disable certain code coverage exclusions automatically. 
; Assertions and FSM are exluded from the code coverage by default
; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
; Or specify comma or space separated list
;AutoExclusionsDisable = fsm,assertions

; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = default

; Default run length
RunLength = 100

; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000

; Control PSL and Verilog Assume directives during simulation
; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
; SimulateAssumeDirectives = 1 

; Control the simulation of PSL and SVA
; These switches can be overridden by the vsim command line switches:
;    -psl, -nopsl, -sva, -nosva.
; Set SimulatePSL = 0 to disable PSL simulation
; Set SimulatePSL = 1 to enable PSL simulation (default)
; SimulatePSL = 1 
; Set SimulateSVA = 0 to disable SVA simulation
; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
; SimulateSVA = 1 

; Directives to license manager can be set either as single value or as
; space separated multi-values:
; vhdl          Immediately reserve a VHDL license
; vlog          Immediately reserve a Verilog license
; plus          Immediately reserve a VHDL and Verilog license
; nomgc         Do not look for Mentor Graphics Licenses
; nomti         Do not look for Model Technology Licenses
; noqueue       Do not wait in the license queue when a license is not available
; viewsim       Try for viewer license but accept simulator license(s) instead
;               of queuing for viewer license (PE ONLY)
; noviewer	Disable checkout of msimviewer and vsim-viewer license 
;		features (PE ONLY)
; noslvhdl	Disable checkout of qhsimvh and vsim license features
; noslvlog	Disable checkout of qhsimvl and vsimvlog license features
; nomix		Disable checkout of msimhdlmix and hdlmix license features
; nolnl		Disable checkout of msimhdlsim and hdlsim license features
; mixedonly	Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license 
;		features
; lnlonly	Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
;		hdlmix license features
; Single value:
; License = plus
; Multi-value:
; License = noqueue plus

; Stop the simulator after a VHDL/Verilog immediate assertion message
; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
BreakOnAssertion = 3

; VHDL assertion Message Format
; %S - Severity Level 
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %i - Instance pathname with process
; %O - Process name
; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
; %P - Instance or Region path without leaf process
; %F - File
; %L - Line number of assertion or, if assertion is in a subprogram, line
;      from which the call is made
; %% - Print '%' character
; If specific format for assertion level is defined, use its format.
; If specific format is not defined for assertion level:
; - and if failure occurs during elaboration, use MessageFormatBreakLine;
; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
;   level), use MessageFormatBreak;
; - otherwise, use MessageFormat.
; MessageFormatBreakLine = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F Line: %L\n"
; MessageFormatBreak     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
; MessageFormat          = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
; MessageFormatNote      = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
; MessageFormatWarning   = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
; MessageFormatError     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
; MessageFormatFail      = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
; MessageFormatFatal     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"

; Error File - alternate file for storing error messages
; ErrorFile = error.log


; Simulation Breakpoint messages
; This flag controls the display of function names when reporting the location
; where the simulator stops do to a breakpoint or fatal error.
; Example w/function name:  # Break in Process ctr at counter.vhd line 44
; Example wo/function name: # Break at counter.vhd line 44
ShowFunctions = 1

; Default radix for all windows and commands.
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic

; VSIM Startup command
; Startup = do startup.do

; VSIM Shutdown file
; Filename to save u/i formats and configurations.
; ShutdownFile = restart.do
; To explicitly disable auto save:
; ShutdownFile = --disable-auto-save

; File for saving command transcript
TranscriptFile = transcript

; File for saving command history
; CommandHistory = cmdhist.log

; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /

; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example: sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :

; Specify a unique path separator for the Signal Spy set of functions. 
; The default will be to use the PathSeparator variable.
; Must not be the same character as DatasetSeparator.
; SignalSpyPathSeparator = /

; Used to control parsing of HDL identifiers input to the tool.
; This includes CLI commands, vsim/vopt/vlog/vcom options,
; string arguments to FLI/VPI/DPI calls, etc.
; If set to 1, accept either Verilog escaped Id syntax or
; VHDL extended id syntax, regardless of source language.