modelsim.ini

频率扫描的VHDL完整代码

; Copyright 1991-2010 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;   

[Library]
others = $MODEL_TECH/../modelsim.ini
;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers       // Source files only for this release
;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
;mvc_lib = $MODEL_TECH/../mvc_lib

secureip = d:\Xilinx\12.4\ISE_DS\ISE\verilog\mti_se\6.5e\nt/secureip
unisim = d:\Xilinx\12.4\ISE_DS\ISE\vhdl\mti_se\6.5e\nt/unisim
unimacro = d:\Xilinx\12.4\ISE_DS\ISE\vhdl\mti_se\6.5e\nt/unimacro
unisims_ver = d:\Xilinx\12.4\ISE_DS\ISE\verilog\mti_se\6.5e\nt/unisims_ver
unimacro_ver = d:\Xilinx\12.4\ISE_DS\ISE\verilog\mti_se\6.5e\nt/unimacro_ver
simprim = d:\Xilinx\12.4\ISE_DS\ISE\vhdl\mti_se\6.5e\nt/simprim
simprims_ver = d:\Xilinx\12.4\ISE_DS\ISE\verilog\mti_se\6.5e\nt/simprims_ver
xilinxcorelib = d:\Xilinx\12.4\ISE_DS\ISE\vhdl\mti_se\6.5e\nt/xilinxcorelib
xilinxcorelib_ver = d:\Xilinx\12.4\ISE_DS\ISE\verilog\mti_se\6.5e\nt/xilinxcorelib_ver
edk = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk
common_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/common_v1_00_a
apu_fpu_v3_10_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/apu_fpu_v3_10_a
apu_fpu_virtex5_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/apu_fpu_virtex5_v1_01_a
axi2axi_connector_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi2axi_connector_v1_00_a
proc_common_v3_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/proc_common_v3_00_a
axi_apb_bridge_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_apb_bridge_v1_00_a
axi_bram_ctrl_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_bram_ctrl_v1_01_a
lib_common_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/lib_common_v1_00_a
axi_lite_ipif_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_lite_ipif_v1_00_a
axi_lite_ipif_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_lite_ipif_v1_01_a
axi_can_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_can_v1_01_a
axi_datamover_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_datamover_v1_00_a
axi_sg_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_sg_v1_00_a
axi_sg_v2_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_sg_v2_00_a
axi_cdma_v2_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_cdma_v2_00_a
axi_dma_v2_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_dma_v2_00_a
axi_slave_burst_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_slave_burst_v1_00_a
emc_common_v5_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/emc_common_v5_00_a
axi_emc_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_emc_v1_00_a
lib_common_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/lib_common_v1_01_a
axi_ethernet_avb_wrap_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_ethernet_avb_wrap_v1_00_a
axi_ethernet_avb_wrap_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_ethernet_avb_wrap_v1_01_a
axi_ethernet_pcs_pma_wrap_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_ethernet_pcs_pma_wrap_v1_00_a
axi_ethernet_pcs_pma_wrap_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_ethernet_pcs_pma_wrap_v1_01_a
axi_ethernet_soft_temac_wrap_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_ethernet_soft_temac_wrap_v1_00_a
axi_ethernet_soft_temac_wrap_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_ethernet_soft_temac_wrap_v1_01_a
axi_ethernet_stat_wrap_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_ethernet_stat_wrap_v1_00_a
axi_ethernet_stat_wrap_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_ethernet_stat_wrap_v1_01_a
axi_ethernet_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_ethernet_v1_01_a
axi_ethernetlite_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_ethernetlite_v1_00_a
axi_ext_master_conn_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_ext_master_conn_v1_00_a
axi_ext_slave_conn_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_ext_slave_conn_v1_00_a
axi_fifo_mm_s_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_fifo_mm_s_v1_00_a
interrupt_control_v2_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/interrupt_control_v2_01_a
axi_gpio_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_gpio_v1_01_a
hwicap_v7_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/hwicap_v7_00_a
axi_hwicap_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_hwicap_v1_00_a
axi_iic_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_iic_v1_01_a
axi_intc_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_intc_v1_01_a
axi_interconnect_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_interconnect_v1_01_a
axi_plbv46_bridge_v2_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_plbv46_bridge_v2_00_a
axi_s6_ddrx_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_s6_ddrx_v1_01_a
axi_spi_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_spi_v1_01_a
sysace_common_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/sysace_common_v1_01_a
axi_sysace_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_sysace_v1_01_a
axi_sysmon_adc_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_sysmon_adc_v1_01_a
axi_timebase_wdt_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_timebase_wdt_v1_01_a
axi_timer_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_timer_v1_01_a
axi_uart16550_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_uart16550_v1_01_a
axi_uartlite_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_uartlite_v1_01_a
axi_usb2_device_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_usb2_device_v1_00_a
axi_v6_ddrx_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_v6_ddrx_v1_01_a
axi_vdma_v2_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/axi_vdma_v2_00_a
block_plus_v1_10_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/block_plus_v1_10_a
block_plus_v1_10_b = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/block_plus_v1_10_b
block_plus_v1_12_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/block_plus_v1_12_a
block_plus_v1_13_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/block_plus_v1_13_a
chipscope_axi_monitor_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/chipscope_axi_monitor_v1_01_a
chipscope_icon_v1_04_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/chipscope_icon_v1_04_a
chipscope_ila_v1_03_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/chipscope_ila_v1_03_a
chipscope_plbv46_iba_v1_03_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/chipscope_plbv46_iba_v1_03_a
chipscope_vio_v1_03_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/chipscope_vio_v1_03_a
clock_generator_v4_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/clock_generator_v4_01_a
csum_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/csum_v1_00_a
dcm_module_v1_00_e = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/dcm_module_v1_00_e
intc_core_v2_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/intc_core_v2_00_a
dcr_intc_v2_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/dcr_intc_v2_00_a
dcr_v29_v1_00_b = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/dcr_v29_v1_00_b
dsbram_if_cntlr_v3_00_c = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/dsbram_if_cntlr_v3_00_c
dsocm_v10_v2_00_b = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/dsocm_v10_v2_00_b
emc_common_v4_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/emc_common_v4_01_a
eth_stat_wrap_v2_02_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/eth_stat_wrap_v2_02_a
eth_stat_wrap_v2_03_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/eth_stat_wrap_v2_03_a
fcb2fsl_bridge_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/fcb2fsl_bridge_v1_00_a
fcb_v10_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/fcb_v10_v1_00_a
fcb_v20_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/fcb_v20_v1_00_a
fit_timer_v1_01_b = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/fit_timer_v1_01_b
fsl_v20_v2_11_c = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/fsl_v20_v2_11_c
hwicap_v4_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/hwicap_v4_00_a
hwicap_v5_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/hwicap_v5_00_a
hwicap_v6_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/hwicap_v6_00_a
proc_common_v2_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/proc_common_v2_00_a
interrupt_control_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/interrupt_control_v1_00_a
isbram_if_cntlr_v3_00_c = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/isbram_if_cntlr_v3_00_c
isocm_v10_v2_00_b = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/isocm_v10_v2_00_b
jtagppc_cntlr_v2_01_c = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/jtagppc_cntlr_v2_01_c
lmb_bram_if_cntlr_v2_10_b = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/lmb_bram_if_cntlr_v2_10_b
lmb_v10_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/lmb_v10_v1_00_a
plbv46_slave_single_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/plbv46_slave_single_v1_01_a
mailbox_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/mailbox_v1_00_a
plbv46_slave_burst_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/plbv46_slave_burst_v1_01_a
mch_plbv46_slave_burst_v2_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/mch_plbv46_slave_burst_v2_01_a
mdm_v2_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/mdm_v2_00_a
mgt_protector_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/mgt_protector_v1_00_a
microblaze_v8_00_b = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/microblaze_v8_00_b
mii_to_rmii_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/mii_to_rmii_v1_01_a
mmcm_module_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/mmcm_module_v1_00_a
mpmc_v6_02_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/mpmc_v6_02_a
mutex_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/mutex_v1_00_a
rdpfifo_v1_01_b = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/rdpfifo_v1_01_b
wrpfifo_v1_01_b = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/wrpfifo_v1_01_b
opb_ipif_v3_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/opb_ipif_v3_01_a
plbv46_master_burst_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/plbv46_master_burst_v1_01_a
pci_arbiter_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/pci_arbiter_v1_00_a
proc_common_v1_00_b = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/proc_common_v1_00_b
plb_v46_v1_05_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/plb_v46_v1_05_a
plbv46_axi_bridge_v2_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/plbv46_axi_bridge_v2_00_a
plbv46_dcr_bridge_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/plbv46_dcr_bridge_v1_01_a
plbv46_master_single_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/plbv46_master_single_v1_01_a
plbv46_master_v1_03_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/plbv46_master_v1_03_a
plbv46_master_v1_04_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/plbv46_master_v1_04_a
wrpfifo_v5_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/wrpfifo_v5_00_a
rdpfifo_v4_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/rdpfifo_v4_01_a
plbv46_slave_v1_03_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/plbv46_slave_v1_03_a
plbv46_pci_v1_03_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/plbv46_pci_v1_03_a
plbv46_slave_v1_04_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/plbv46_slave_v1_04_a
virtex6_pcie_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/virtex6_pcie_v1_01_a
spartan6_pcie_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/spartan6_pcie_v1_01_a
virtex6_pcie_v1_02_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/virtex6_pcie_v1_02_a
spartan6_pcie_v1_02_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/spartan6_pcie_v1_02_a
virtex6_pcie_v1_04_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/virtex6_pcie_v1_04_a
spartan6_pcie_v1_04_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/spartan6_pcie_v1_04_a
virtex6_pcie_v1_05_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/virtex6_pcie_v1_05_a
plbv46_pcie_v4_06_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/plbv46_pcie_v4_06_a
plbv46_slave_v1_02_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/plbv46_slave_v1_02_a
wrpfifo_v5_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/wrpfifo_v5_01_a
rdpfifo_v4_02_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/rdpfifo_v4_02_a
plbv46_slave_v1_05_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/plbv46_slave_v1_05_a
plbv46_plbv46_bridge_v1_03_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/plbv46_plbv46_bridge_v1_03_a
pll_module_v2_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/pll_module_v2_00_a
ppc405_virtex4_v2_01_b = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/ppc405_virtex4_v2_01_b
ppc440_virtex5_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/ppc440_virtex5_v1_01_a
ppc440mc_ddr2_v3_00_b = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/ppc440mc_ddr2_v3_00_b
ppc440mc_ddr2_v3_00_c = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/ppc440mc_ddr2_v3_00_c
proc_sys_reset_v3_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/proc_sys_reset_v3_00_a
proc_utils_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/proc_utils_v1_00_a
soft_temac_wrap_v2_02_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/soft_temac_wrap_v2_02_a
soft_temac_wrap_v2_03_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/soft_temac_wrap_v2_03_a
spartan6_pcie_v1_03_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/spartan6_pcie_v1_03_a
util_bus_split_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/util_bus_split_v1_00_a
util_ds_buf_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/util_ds_buf_v1_01_a
util_flipflop_v1_10_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/util_flipflop_v1_10_a
util_io_mux_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/util_io_mux_v1_00_a
util_reduced_logic_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/util_reduced_logic_v1_00_a
util_vector_logic_v1_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/util_vector_logic_v1_00_a
virtex6_pcie_v1_03_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/virtex6_pcie_v1_03_a
xps_bram_if_cntlr_v1_00_b = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_bram_if_cntlr_v1_00_b
xps_can_v3_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_can_v3_01_a
xps_central_dma_v2_03_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_central_dma_v2_03_a
xps_deltasigma_adc_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_deltasigma_adc_v1_01_a
xps_deltasigma_dac_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_deltasigma_dac_v1_01_a
xps_epc_v1_02_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_epc_v1_02_a
xps_ethernetlite_v4_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_ethernetlite_v4_00_a
xps_gpio_v2_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_gpio_v2_00_a
xps_hwicap_v5_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_hwicap_v5_00_a
xps_iic_v2_03_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_iic_v2_03_a
xps_spi_v2_02_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_spi_v2_02_a
xps_insystem_flash_v1_02_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_insystem_flash_v1_02_a
xps_intc_v2_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_intc_v2_01_a
xps_ll_fifo_v1_02_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_ll_fifo_v1_02_a
xps_ll_temac_v2_03_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_ll_temac_v2_03_a
xps_mch_emc_v3_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_mch_emc_v3_01_a
xps_most_nic_v1_03_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_most_nic_v1_03_a
xps_ps2_v1_01_b = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_ps2_v1_01_b
xps_sysace_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_sysace_v1_01_a
xps_sysmon_adc_v2_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_sysmon_adc_v2_00_a
xps_tft_v2_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_tft_v2_01_a
xps_timebase_wdt_v1_02_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_timebase_wdt_v1_02_a
xps_timer_v1_02_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_timer_v1_02_a
xps_uart16550_v3_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_uart16550_v3_00_a
xps_uartlite_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_uartlite_v1_01_a
xps_usb2_device_v5_00_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_usb2_device_v5_00_a
xps_usb_host_v1_01_a = d:\Xilinx\12.4\ISE_DS\ISE\mti_se\6.5e\nt/edk/xps_usb_host_v1_01_a
[vcom]
; VHDL93 variable selects language version as the default. 
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
; Value of 3 or 2008 for VHDL-2008
VHDL93 = 2002

; Show source line containing error. Default is off.
; Show_source = 1

; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0

; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0

; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0

; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0

; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0

; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0

; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1

; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1

; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1

; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1

; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0

; Turn off PSL assertion warning messages. Default is to show warnings.
; Show_PslChecksWarnings = 0

; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0

; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1

; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1

; Treat as errors:
;   case statement static warnings
;   warnings caused by aggregates that are not locally static
; Overrides NoCaseStaticError, NoOthersStaticError settings.
; PedanticErrors = 1

; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1

; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1

; Turn on some limited synthesis rule compliance checking. Checks only: