idea_en_top.vhd

IDEA加密运算模块

  end if;
  end process;
 
 
  PT_1(63 downto 0) <= (visual_C38_O);
   process (S45 , PT_X , PT_N , I4 , CTRL)
   begin
     case CTRL(1 downto 0) is
       when "00" =>
         visual_C38_O <=  S45(63 downto 0);
       when "01" =>
         visual_C38_O <=  PT_X(63 downto 0);
       when "10" =>
         visual_C38_O <=  PT_N(63 downto 0);
       when others =>
         visual_C38_O <=  I4(63 downto 0);
     end case;
   end process;
 
 
  I4(63 downto 0) <= X"0000000000000000";
 
 
  S45(63 downto 0) <= (visual_C40_Q);
 
 
  process (CLK)
  begin
  if (CLK'event and CLK = '1') then
    if (RST = '0') then
      visual_C40_Q <= (others => '0');
    else
      if (ZO = '1') then
        visual_C40_Q <= (PT(63 downto 0));
      end if;
   end if;
  end if;
  end process;
 
end ED_64_L;
----------------------------------------------------
--  
--  Library Name :  Idea_vhd_100M
--  Unit    Name :  ED_64
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_UNSIGNED.all;
entity ED_64 is
  port (
        BUSY : out std_logic;
        CLK : in std_logic;
        E : in std_logic;
        OV : out std_logic;
        PT : in std_logic_vector(63 downto 0 );
        Q : out std_logic_vector(63 downto 0 );
        RST : in std_logic;
        ZY_BUS_1 : in std_logic_vector(95 downto 0 );
        ZY_BUS_2 : in std_logic_vector(95 downto 0 );
        ZY_BUS_3 : in std_logic_vector(95 downto 0 );
        ZY_BUS_4 : in std_logic_vector(95 downto 0 );
        ZY_BUS_5 : in std_logic_vector(95 downto 0 );
        ZY_BUS_6 : in std_logic_vector(95 downto 0 );
        ZY_BUS_7 : in std_logic_vector(95 downto 0 );
        ZY_BUS_8 : in std_logic_vector(95 downto 0 );
        ZY_BUS_9 : in std_logic_vector(63 downto 0 )
        );
 
 
end ED_64;
 
 
use work.all;
architecture ED_64 of ED_64 is
 
  signal CTRL : std_logic_vector(1 downto 0 );
  signal E_RUS : std_logic;
  signal I2 : std_logic_vector(95 downto 0 );
  signal O : std_logic_vector(95 downto 0 );
  signal S10 : std_logic_vector(31 downto 0 );
  signal ZY_CTRL : std_logic_vector(3 downto 0 );
  signal ZY_IN : std_logic_vector(95 downto 0 );
  component ED_64_L
      port (
            CLK : in std_logic;
            CTRL : in std_logic_vector(1 downto 0 );
            OV_E : in std_logic;
            PT : in std_logic_vector(63 downto 0 );
            Q : out std_logic_vector(63 downto 0 );
            RST : in std_logic;
            ZO : in std_logic;
            ZY : in std_logic_vector(95 downto 0 )
            );
  end component;
  component ED_64_L_CT
      port (
            CLK : in std_logic;
            RST : in std_logic;
            ZY_CTRL : out std_logic_vector(3 downto 0 );
            CTRL : out std_logic_vector(1 downto 0 );
            OV : out std_logic;
            ZO : in std_logic;
            BUSY : out std_logic;
            E_RUS : out std_logic
            );
  end component;
  signal visual_C50_O : std_logic_vector(96 - 1 downto 0 );
  signal visual_C2_O : std_logic_vector(96 - 1 downto 0 );
 
  -- Start Configuration Specification
  -- ++ for all : ED_64_L use entity work.ED_64_L(ED_64_L);
  -- ++ for all : ED_64_L_CT use entity work.ED_64_L_CT(ED_64_L_CT);
  -- End Configuration Specification
 
begin
 
  inst_ED_64_L: ED_64_L
    port map (
              CLK => CLK,
              CTRL => CTRL(1 downto 0),
              OV_E => E_RUS,
              PT => PT(63 downto 0),
              Q => Q(63 downto 0),
              RST => RST,
              ZO => E,
              ZY => ZY_IN(95 downto 0)
              );
 
  inst_ED_64_L_CT: ED_64_L_CT
    port map (
              CLK => CLK,
              RST => RST,
              ZY_CTRL => ZY_CTRL(3 downto 0),
              CTRL => CTRL(1 downto 0),
              OV => OV,
              ZO => E,
              BUSY => BUSY,
              E_RUS => E_RUS
              );
 
  O(95 downto 0) <= (visual_C50_O);
   process (ZY_BUS_1 , ZY_BUS_2 , ZY_BUS_3 , ZY_BUS_4 , ZY_BUS_5 , ZY_BUS_6 , ZY_BUS_7 , ZY_BUS_8 , ZY_CTRL)
   begin
     case ZY_CTRL(2 downto 0) is
       when "000" =>
         visual_C50_O <=  ZY_BUS_1(95 downto 0);
       when "001" =>
         visual_C50_O <=  ZY_BUS_2(95 downto 0);
       when "010" =>
         visual_C50_O <=  ZY_BUS_3(95 downto 0);
       when "011" =>
         visual_C50_O <=  ZY_BUS_4(95 downto 0);
       when "100" =>
         visual_C50_O <=  ZY_BUS_5(95 downto 0);
       when "101" =>
         visual_C50_O <=  ZY_BUS_6(95 downto 0);
       when "110" =>
         visual_C50_O <=  ZY_BUS_7(95 downto 0);
       when others =>
         visual_C50_O <=  ZY_BUS_8(95 downto 0);
     end case;
   end process;
 
 
  ZY_IN(95 downto 0) <= (visual_C2_O);
   process (O , I2 , ZY_CTRL)
   begin
     case ZY_CTRL(3) is
       when '0' =>
         visual_C2_O <=  O(95 downto 0);
       when others =>
         visual_C2_O <=  I2(95 downto 0);
     end case;
   end process;
 
 
  S10(31 downto 0) <= X"00000000";
 
 
  I2(95 downto 32) <= ZY_BUS_9(63 downto 0);
  I2(31 downto 0) <= S10(31 downto 0);
end ED_64;
----------------------------------------------------
--  
--  Library Name :  Idea_vhd_100M
--  Unit    Name :  IDEA_EN
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
entity IDEA_EN is
  port (
        BUSY : out std_logic;
        CLK : in std_logic;
        D : in std_logic_vector(63 downto 0 );
        E : in std_logic;
        EKLD : in std_logic;
        OV : out std_logic;
        Q : out std_logic_vector(63 downto 0 );
        RST : in std_logic
        );
 
 
end IDEA_EN;
 
 
use work.all;
architecture IDEA_EN of IDEA_EN is
 
  signal KEY_128 : std_logic_vector(127 downto 0 );
  signal Q_1 : std_logic_vector(63 downto 0 );
  signal Q_2 : std_logic_vector(63 downto 0 );
  signal ZY_BUS_1 : std_logic_vector(95 downto 0 );
  signal ZY_BUS_2 : std_logic_vector(95 downto 0 );
  signal ZY_BUS_3 : std_logic_vector(95 downto 0 );
  signal ZY_BUS_4 : std_logic_vector(95 downto 0 );
  signal ZY_BUS_5 : std_logic_vector(95 downto 0 );
  signal ZY_BUS_6 : std_logic_vector(95 downto 0 );
  signal ZY_BUS_7 : std_logic_vector(95 downto 0 );
  signal ZY_BUS_8 : std_logic_vector(95 downto 0 );
  signal ZY_BUS_9 : std_logic_vector(63 downto 0 );
  component ED_64
      port (
            BUSY : out std_logic;
            CLK : in std_logic;
            E : in std_logic;
            OV : out std_logic;
            PT : in std_logic_vector(63 downto 0 );
            Q : out std_logic_vector(63 downto 0 );
            RST : in std_logic;
            ZY_BUS_1 : in std_logic_vector(95 downto 0 );
            ZY_BUS_2 : in std_logic_vector(95 downto 0 );
            ZY_BUS_3 : in std_logic_vector(95 downto 0 );
            ZY_BUS_4 : in std_logic_vector(95 downto 0 );
            ZY_BUS_5 : in std_logic_vector(95 downto 0 );
            ZY_BUS_6 : in std_logic_vector(95 downto 0 );
            ZY_BUS_7 : in std_logic_vector(95 downto 0 );
            ZY_BUS_8 : in std_logic_vector(95 downto 0 );
            ZY_BUS_9 : in std_logic_vector(63 downto 0 )
            );
  end component;
  component EN_KEY_GEN
      port (
            KEY_IN : in std_logic_vector(127 downto 0 );
            ZY_BUS_1 : out std_logic_vector(95 downto 0 );
            ZY_BUS_2 : out std_logic_vector(95 downto 0 );
            ZY_BUS_3 : out std_logic_vector(95 downto 0 );
            ZY_BUS_4 : out std_logic_vector(95 downto 0 );
            ZY_BUS_5 : out std_logic_vector(95 downto 0 );
            ZY_BUS_6 : out std_logic_vector(95 downto 0 );
            ZY_BUS_7 : out std_logic_vector(95 downto 0 );
            ZY_BUS_8 : out std_logic_vector(95 downto 0 );
            ZY_BUS_9 : out std_logic_vector(63 downto 0 )
            );
  end component;
  signal visual_C33_Q : std_logic_vector(64 - 1 downto 0 );
  signal visual_C34_Q : std_logic_vector(64 - 1 downto 0 );
 
  -- Start Configuration Specification
  -- ++ for all : ED_64 use entity work.ED_64(ED_64);
  -- ++ for all : EN_KEY_GEN use entity work.EN_KEY_GEN(EN_KEY_GEN);
  -- End Configuration Specification
 
begin
 
  C38: ED_64
    port map (
              BUSY => BUSY,
              CLK => CLK,
              E => E,
              OV => OV,
              PT => D(63 downto 0),
              Q => Q(63 downto 0),
              RST => RST,
              ZY_BUS_1 => ZY_BUS_1(95 downto 0),
              ZY_BUS_2 => ZY_BUS_2(95 downto 0),
              ZY_BUS_3 => ZY_BUS_3(95 downto 0),
              ZY_BUS_4 => ZY_BUS_4(95 downto 0),
              ZY_BUS_5 => ZY_BUS_5(95 downto 0),
              ZY_BUS_6 => ZY_BUS_6(95 downto 0),
              ZY_BUS_7 => ZY_BUS_7(95 downto 0),
              ZY_BUS_8 => ZY_BUS_8(95 downto 0),
              ZY_BUS_9 => ZY_BUS_9(63 downto 0)
              );
 
  C48: EN_KEY_GEN
    port map (
              KEY_IN => KEY_128(127 downto 0),
              ZY_BUS_1 => ZY_BUS_1(95 downto 0),
              ZY_BUS_2 => ZY_BUS_2(95 downto 0),
              ZY_BUS_3 => ZY_BUS_3(95 downto 0),
              ZY_BUS_4 => ZY_BUS_4(95 downto 0),
              ZY_BUS_5 => ZY_BUS_5(95 downto 0),
              ZY_BUS_6 => ZY_BUS_6(95 downto 0),
              ZY_BUS_7 => ZY_BUS_7(95 downto 0),
              ZY_BUS_8 => ZY_BUS_8(95 downto 0),
              ZY_BUS_9 => ZY_BUS_9(63 downto 0)
              );
 
  Q_1(63 downto 0) <= (visual_C33_Q);
 
 
  process (CLK)
  begin
  if (CLK'event and CLK = '1') then
    if (RST = '0') then
      visual_C33_Q <= (others => '0');
    else
      if (EKLD = '1') then
        visual_C33_Q <= (Q_2(63 downto 0));
      end if;
   end if;
  end if;
  end process;
 
 
  Q_2(63 downto 0) <= (visual_C34_Q);
 
 
  process (CLK)
  begin
  if (CLK'event and CLK = '1') then
    if (RST = '0') then
      visual_C34_Q <= (others => '0');
    else
      if (EKLD = '1') then
        visual_C34_Q <= (D(63 downto 0));
      end if;
   end if;
  end if;
  end process;
 
 
  KEY_128(127 downto 64) <= Q_1(63 downto 0);
  KEY_128(63 downto 0) <= Q_2(63 downto 0);
end IDEA_EN;
----------------------------------------------------
--  
--  Library Name :  Idea_vhd_100M
--  Unit    Name :  IDEA_EN_TOP
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
entity IDEA_EN_TOP is
  port (
        BUSY : out std_logic;
        CLK : in std_logic;
        D : in std_logic_vector(63 downto 0 );
        E_PT : in std_logic;
        EKLD : in std_logic;
        OVER : out std_logic;
        QOUT : out std_logic_vector(63 downto 0 );
        RST : in std_logic
        );
 
 
end IDEA_EN_TOP;
 
 
use work.all;
architecture IDEA_EN_TOP of IDEA_EN_TOP is
 
  component IDEA_EN
      port (
            BUSY : out std_logic;
            CLK : in std_logic;
            D : in std_logic_vector(63 downto 0 );
            E : in std_logic;
            EKLD : in std_logic;
            OV : out std_logic;
            Q : out std_logic_vector(63 downto 0 );
            RST : in std_logic
            );
  end component;
 
  -- Start Configuration Specification
  -- ++ for all : IDEA_EN use entity work.IDEA_EN(IDEA_EN);
  -- End Configuration Specification
 
begin
 
  IDEA_TOP: IDEA_EN
    port map (
              BUSY => BUSY,
              CLK => CLK,
              D => D(63 downto 0),
              E => E_PT,
              EKLD => EKLD,
              OV => OVER,
              Q => QOUT(63 downto 0),
              RST => RST
              );
end IDEA_EN_TOP;