idea_en_top.vhd

IDEA加密运算模块

 
    visual_C0_tmp_a <= (A(15 downto 0));
    visual_C0_tmp_b <= (B(15 downto 0));
    visual_C0_sum_int <= (unsigned('0' & visual_C0_tmp_a)
       + unsigned('0' & visual_C0_tmp_b));
 
       O(15 downto 0) <= (visual_C0_sum_int(16 - 1 downto 0));
 
end MADD_16;
----------------------------------------------------
--  
--  Library Name :  Idea_vhd_100M
--  Unit    Name :  MMUL_16A1_min
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_UNSIGNED.all;
entity MMUL_16A1_min is
  port (
        A : in std_logic_vector(15 downto 0 );
        B : in std_logic_vector(15 downto 0 );
        MOUT : out std_logic_vector(15 downto 0 )
        );
 
 
end MMUL_16A1_min;
 
 
architecture MMUL_16A1_min of MMUL_16A1_min is
 
  signal A_0 : std_logic;
  signal ABI : std_logic_vector(15 downto 0 );
  signal B_0 : std_logic;
  signal CO : std_logic;
  signal I1 : std_logic_vector(16 downto 0 );
  signal MOUT1 : std_logic_vector(15 downto 0 );
  signal O : std_logic_vector(31 downto 0 );
  signal S10 : std_logic_vector(16 downto 0 );
  signal S11 : std_logic_vector(16 downto 0 );
  signal S13 : std_logic_vector(15 downto 0 );
  signal S3 : std_logic;
  signal S9 : std_logic_vector(15 downto 0 );
  signal SEL_L : std_logic;
  signal visual_C3_dif_int : std_logic_vector(16 downto 0 );
  signal visual_C3_tmp_a : std_logic_vector(16 - 1 downto 0 );
  signal visual_C3_tmp_b : std_logic_vector(16 - 1 downto 0 );
  constant visual_C3_zero : std_logic_vector(16 - 1 downto 0 ) := (others  =>
                                                  '0');
  signal visual_C14_tmp_a : std_logic_vector(16 - 1 downto 0 );
  signal visual_C14_tmp_b : std_logic_vector(16 - 1 downto 0 );
  signal visual_C14_prd_int : std_logic_vector(32 - 1 downto 0 );
  signal visual_C0_O : std_logic_vector(16 - 1 downto 0 );
  signal visual_C58_O : std_logic_vector(16 - 1 downto 0 );
  signal visual_C67_O : std_logic_vector(16 - 1 downto 0 );
  signal visual_C5_dif_int : std_logic_vector(17 downto 0 );
  signal visual_C5_tmp_a : std_logic_vector(17 - 1 downto 0 );
  signal visual_C5_tmp_b : std_logic_vector(17 - 1 downto 0 );
  constant visual_C5_zero : std_logic_vector(17 - 1 downto 0 ) := (others  =>
                                                  '0');
 
 
begin
 
 
    visual_C3_tmp_a <= (O(15 downto 0));
    visual_C3_tmp_b <= (O(31 downto 16));
    visual_C3_dif_int <= (unsigned('0' & visual_C3_tmp_a)
       - unsigned('0' & visual_C3_tmp_b));
 
       S13(15 downto 0) <= (visual_C3_dif_int(16 - 1 downto 0));
 
       CO <= (visual_C3_dif_int(16));
 
 
  visual_C14_tmp_a <= (A(15 downto 0));
  visual_C14_tmp_b <= (B(15 downto 0));
 
 
  visual_C14_prd_int <= (unsigned(visual_C14_tmp_a) * unsigned(visual_C14_tmp_b));
 
 
  O(31 downto 0) <= (visual_C14_prd_int(16 + 16 - 1 downto 0));
 
  MOUT1(15 downto 0) <= (visual_C0_O);
   process (S13 , S9 , CO)
   begin
     case CO is
       when '0' =>
         visual_C0_O <=  S13(15 downto 0);
       when others =>
         visual_C0_O <=  S9(15 downto 0);
     end case;
   end process;
 
 
   A_0 <= ( A(15)) or ( A(14)) or ( A(13)) or ( A(12)) or ( A(11))
            or ( A(10)) or ( A(9)) or ( A(8)) or ( A(7)) or ( A(6))
            or ( A(5)) or ( A(4)) or ( A(3)) or ( A(2)) or ( A(1))
            or ( A(0));
 
 
   B_0 <= ( B(15)) or ( B(14)) or ( B(13)) or ( B(12)) or ( B(11))
            or ( B(10)) or ( B(9)) or ( B(8)) or ( B(7)) or ( B(6))
            or ( B(5)) or ( B(4)) or ( B(3)) or ( B(2)) or ( B(1))
            or ( B(0));
 
 
  ABI(15 downto 0) <= (visual_C58_O);
   process (A , B , B_0)
   begin
     case B_0 is
       when '0' =>
         visual_C58_O <=  A(15 downto 0);
       when others =>
         visual_C58_O <=  B(15 downto 0);
     end case;
   end process;
 
 
  MOUT(15 downto 0) <= (visual_C67_O);
   process (S11 , MOUT1 , SEL_L)
   begin
     case SEL_L is
       when '0' =>
         visual_C67_O <=  S11(15 downto 0);
       when others =>
         visual_C67_O <=  MOUT1(15 downto 0);
     end case;
   end process;
 
 
   SEL_L <= ( A_0) and ( B_0);
 
 
  S3 <= '0';
 
  I1(16) <= S3;
  I1(15 downto 0) <= ABI(15 downto 0);
 
 
  S9(15 downto 0) <= (unsigned((S13(15 downto 0))) + 1);
 
 
  S10(16 downto 0) <= "10000000000000001";
 
 
 
    visual_C5_tmp_a <= (S10(16 downto 0));
    visual_C5_tmp_b <= (I1(16 downto 0));
    visual_C5_dif_int <= (unsigned('0' & visual_C5_tmp_a)
       - unsigned('0' & visual_C5_tmp_b));
 
       S11(16 downto 0) <= (visual_C5_dif_int(17 - 1 downto 0));
 
end MMUL_16A1_min;
----------------------------------------------------
--  
--  Library Name :  Idea_vhd_100M
--  Unit    Name :  ED_64_L
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
entity ED_64_L is
  port (
        CLK : in std_logic;
        CTRL : in std_logic_vector(1 downto 0 );
        OV_E : in std_logic;
        PT : in std_logic_vector(63 downto 0 );
        Q : out std_logic_vector(63 downto 0 );
        RST : in std_logic;
        ZO : in std_logic;
        ZY : in std_logic_vector(95 downto 0 )
        );
 
 
end ED_64_L;
 
 
use work.all;
architecture ED_64_L of ED_64_L is
 
  signal I4 : std_logic_vector(63 downto 0 );
  signal MADD_1 : std_logic_vector(15 downto 0 );
  signal MADD_2 : std_logic_vector(15 downto 0 );
  signal MADD_3 : std_logic_vector(15 downto 0 );
  signal MADD_4 : std_logic_vector(15 downto 0 );
  signal MMUL_1 : std_logic_vector(15 downto 0 );
  signal MMUL_2 : std_logic_vector(15 downto 0 );
  signal MMUL_3 : std_logic_vector(15 downto 0 );
  signal MMUL_4 : std_logic_vector(15 downto 0 );
  signal O : std_logic_vector(15 downto 0 );
  signal PT_1 : std_logic_vector(63 downto 0 );
  signal PT_N : std_logic_vector(63 downto 0 );
  signal PT_X : std_logic_vector(63 downto 0 );
  signal S45 : std_logic_vector(63 downto 0 );
  signal S54 : std_logic_vector(15 downto 0 );
  signal S55 : std_logic_vector(15 downto 0 );
  signal S56 : std_logic_vector(15 downto 0 );
  signal S66 : std_logic_vector(63 downto 0 );
  signal XOR_1 : std_logic_vector(15 downto 0 );
  signal XOR_2 : std_logic_vector(15 downto 0 );
  signal XOR_3 : std_logic_vector(15 downto 0 );
  signal XOR_4 : std_logic_vector(15 downto 0 );
  signal XOR_5 : std_logic_vector(15 downto 0 );
  signal XOR_6 : std_logic_vector(15 downto 0 );
  component MMUL_16A1_min
      port (
            A : in std_logic_vector(15 downto 0 );
            B : in std_logic_vector(15 downto 0 );
            MOUT : out std_logic_vector(15 downto 0 )
            );
  end component;
  component MADD_16
      port (
            A : in std_logic_vector(15 downto 0 );
            B : in std_logic_vector(15 downto 0 );
            O : out std_logic_vector(15 downto 0 )
            );
  end component;
  signal visual_C38_O : std_logic_vector(64 - 1 downto 0 );
  signal visual_C40_Q : std_logic_vector(64 - 1 downto 0 );
  signal visual_C76_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C77_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C78_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C79_Q : std_logic_vector(16 - 1 downto 0 );
  signal visual_C80_Q : std_logic_vector(64 - 1 downto 0 );
 
  -- Start Configuration Specification
  -- ++ for all : MMUL_16A1_min use entity work.MMUL_16A1_min(MMUL_16A1_min);
  -- ++ for all : MADD_16 use entity work.MADD_16(MADD_16);
  -- End Configuration Specification
 
begin
 
  C0: MMUL_16A1_min
    port map (
              A => ZY(95 downto 80),
              B => PT_1(63 downto 48),
              MOUT => MMUL_1(15 downto 0)
              );
 
  C1: MMUL_16A1_min
    port map (
              A => ZY(47 downto 32),
              B => PT_1(15 downto 0),
              MOUT => MMUL_2(15 downto 0)
              );
 
  C2: MMUL_16A1_min
    port map (
              A => ZY(31 downto 16),
              B => XOR_1(15 downto 0),
              MOUT => MMUL_3(15 downto 0)
              );
 
  C3: MMUL_16A1_min
    port map (
              A => ZY(15 downto 0),
              B => MADD_3(15 downto 0),
              MOUT => MMUL_4(15 downto 0)
              );
 
  C85: MADD_16
    port map (
              A => ZY(79 downto 64),
              B => PT_1(47 downto 32),
              O => MADD_1(15 downto 0)
              );
 
  C86: MADD_16
    port map (
              A => ZY(63 downto 48),
              B => PT_1(31 downto 16),
              O => MADD_2(15 downto 0)
              );
 
  C87: MADD_16
    port map (
              A => XOR_2(15 downto 0),
              B => MMUL_3(15 downto 0),
              O => MADD_3(15 downto 0)
              );
 
  C88: MADD_16
    port map (
              A => MMUL_3(15 downto 0),
              B => MMUL_4(15 downto 0),
              O => MADD_4(15 downto 0)
              );
 
   XOR_1(15 downto 0) <= ( MMUL_1(15 downto 0)) xor ( MADD_2(15 downto 0));
 
 
   S54(15 downto 0) <= ( MADD_1(15 downto 0)) xor ( MADD_4(15 downto 0));
 
 
   XOR_2(15 downto 0) <= ( MADD_1(15 downto 0)) xor ( MMUL_2(15 downto 0));
 
 
   S55(15 downto 0) <= ( MADD_2(15 downto 0)) xor ( MMUL_4(15 downto 0));
 
 
   O(15 downto 0) <= ( MMUL_1(15 downto 0)) xor ( MMUL_4(15 downto 0));
 
 
   S56(15 downto 0) <= ( MMUL_2(15 downto 0)) xor ( MADD_4(15 downto 0));
 
 
  PT_N(63 downto 48) <= XOR_3(15 downto 0);
  PT_N(47 downto 32) <= XOR_4(15 downto 0);
  PT_N(31 downto 16) <= XOR_5(15 downto 0);
  PT_N(15 downto 0) <= XOR_6(15 downto 0);
 
  PT_X(63 downto 48) <= XOR_3(15 downto 0);
  PT_X(47 downto 32) <= XOR_5(15 downto 0);
  PT_X(31 downto 16) <= XOR_4(15 downto 0);
  PT_X(15 downto 0) <= XOR_6(15 downto 0);
 
  S66(63 downto 48) <= MMUL_1(15 downto 0);
  S66(47 downto 32) <= MADD_1(15 downto 0);
  S66(31 downto 16) <= MADD_2(15 downto 0);
  S66(15 downto 0) <= MMUL_2(15 downto 0);
 
  XOR_3(15 downto 0) <= (visual_C76_Q);
 
 
  process (CLK)
  begin
  if (CLK'event and CLK = '1') then
    if (RST = '0') then
      visual_C76_Q <= (others => '0');
    else      visual_C76_Q <= (O(15 downto 0));
 
   end if;
  end if;
  end process;
 
 
  XOR_4(15 downto 0) <= (visual_C77_Q);
 
 
  process (CLK)
  begin
  if (CLK'event and CLK = '1') then
    if (RST = '0') then
      visual_C77_Q <= (others => '0');
    else      visual_C77_Q <= (S54(15 downto 0));
 
   end if;
  end if;
  end process;
 
 
  XOR_5(15 downto 0) <= (visual_C78_Q);
 
 
  process (CLK)
  begin
  if (CLK'event and CLK = '1') then
    if (RST = '0') then
      visual_C78_Q <= (others => '0');
    else      visual_C78_Q <= (S55(15 downto 0));
 
   end if;
  end if;
  end process;
 
 
  XOR_6(15 downto 0) <= (visual_C79_Q);
 
 
  process (CLK)
  begin
  if (CLK'event and CLK = '1') then
    if (RST = '0') then
      visual_C79_Q <= (others => '0');
    else      visual_C79_Q <= (S56(15 downto 0));
 
   end if;
  end if;
  end process;
 
 
  Q(63 downto 0) <= (visual_C80_Q);
 
 
  process (CLK)
  begin
  if (CLK'event and CLK = '1') then
    if (RST = '0') then
      visual_C80_Q <= (others => '0');
    else
      if (OV_E = '1') then
        visual_C80_Q <= (S66(63 downto 0));
      end if;
   end if;