des3_top.vhd

3des10m性能优化设计代码

  smm61 <= Kt(2);
  smm62 <= Kt(1);
  smm63 <= Kt(0);
  smm60 <= Kt(3);
  smm57 <= Kt(6);
  smm58 <= Kt(5);
  smm59 <= Kt(4);
  smm56 <= Kt(7);
  smm53 <= Kt(10);
  smm54 <= Kt(9);
  smm55 <= Kt(8);
  smm52 <= Kt(11);
  smm51 <= Kt(12);
  smm50 <= Kt(13);
  smm49 <= Kt(14);
 
  QSHIFTdd1(55 downto 28) <= SHIFTOUTLdd1(27 downto 0);
  QSHIFTdd1(27 downto 0) <= SHIFTOUTRdd1(27 downto 0);
 
  SHIFTOUTLdd1(27 downto 1) <= Spp7(54 downto 28);
  SHIFTOUTLdd1(0) <= Spp7(55);
 
  SHIFTOUTRdd1(27 downto 1) <= Spp7(26 downto 0);
  SHIFTOUTRdd1(0) <= Spp7(27);
 
  QSHIFTdd2(55 downto 28) <= SHIFTOUTLdd2(27 downto 0);
  QSHIFTdd2(27 downto 0) <= SHIFTOUTRdd2(27 downto 0);
 
  QSHIFTdd3(55 downto 28) <= SHIFTOUTLdd3(27 downto 0);
  QSHIFTdd3(27 downto 0) <= SHIFTOUTRdd3(27 downto 0);
 
  QSHIFTdd4(55 downto 28) <= SHIFTOUTLdd4(27 downto 0);
  QSHIFTdd4(27 downto 0) <= SHIFTOUTRdd4(27 downto 0);
 
  QSHIFTdd5(55 downto 28) <= SHIFTOUTLdd5(27 downto 0);
  QSHIFTdd5(27 downto 0) <= SHIFTOUTRdd5(27 downto 0);
 
  QSHIFTdd6(55 downto 28) <= SHIFTOUTLdd6(27 downto 0);
  QSHIFTdd6(27 downto 0) <= SHIFTOUTRdd6(27 downto 0);
 
  QSHIFTdd7(55 downto 28) <= SHIFTOUTLdd7(27 downto 0);
  QSHIFTdd7(27 downto 0) <= SHIFTOUTRdd7(27 downto 0);
 
  QSHIFTdd8(55 downto 28) <= SHIFTOUTLdd8(27 downto 0);
  QSHIFTdd8(27 downto 0) <= SHIFTOUTRdd8(27 downto 0);
 
  QSHIFTdd9(55 downto 28) <= SHIFTOUTLdd9(27 downto 0);
  QSHIFTdd9(27 downto 0) <= SHIFTOUTRdd9(27 downto 0);
 
  QSHIFTdd10(55 downto 28) <= SHIFTOUTLdd10(27 downto 0);
  QSHIFTdd10(27 downto 0) <= SHIFTOUTRdd10(27 downto 0);
 
  SHIFTOUTRdd2(27 downto 1) <= SHIFTOUTRdd1(26 downto 0);
  SHIFTOUTRdd2(0) <= SHIFTOUTRdd1(27);
 
  SHIFTOUTLdd2(27 downto 1) <= SHIFTOUTLdd1(26 downto 0);
  SHIFTOUTLdd2(0) <= SHIFTOUTLdd1(27);
 
  SHIFTOUTRdd3(27 downto 2) <= SHIFTOUTRdd2(25 downto 0);
  SHIFTOUTRdd3(1 downto 0) <= SHIFTOUTRdd2(27 downto 26);
 
  SHIFTOUTLdd3(27 downto 2) <= SHIFTOUTLdd2(25 downto 0);
  SHIFTOUTLdd3(1 downto 0) <= SHIFTOUTLdd2(27 downto 26);
 
  SHIFTOUTRdd4(27 downto 2) <= SHIFTOUTRdd3(25 downto 0);
  SHIFTOUTRdd4(1 downto 0) <= SHIFTOUTRdd3(27 downto 26);
 
  SHIFTOUTLdd4(27 downto 2) <= SHIFTOUTLdd3(25 downto 0);
  SHIFTOUTLdd4(1 downto 0) <= SHIFTOUTLdd3(27 downto 26);
 
  SHIFTOUTRdd5(27 downto 2) <= SHIFTOUTRdd4(25 downto 0);
  SHIFTOUTRdd5(1 downto 0) <= SHIFTOUTRdd4(27 downto 26);
 
  SHIFTOUTLdd5(27 downto 2) <= SHIFTOUTLdd4(25 downto 0);
  SHIFTOUTLdd5(1 downto 0) <= SHIFTOUTLdd4(27 downto 26);
 
  SHIFTOUTRdd6(27 downto 2) <= SHIFTOUTRdd5(25 downto 0);
  SHIFTOUTRdd6(1 downto 0) <= SHIFTOUTRdd5(27 downto 26);
 
  SHIFTOUTLdd6(27 downto 2) <= SHIFTOUTLdd5(25 downto 0);
  SHIFTOUTLdd6(1 downto 0) <= SHIFTOUTLdd5(27 downto 26);
 
  SHIFTOUTRdd7(27 downto 2) <= SHIFTOUTRdd6(25 downto 0);
  SHIFTOUTRdd7(1 downto 0) <= SHIFTOUTRdd6(27 downto 26);
 
  SHIFTOUTLdd7(27 downto 2) <= SHIFTOUTLdd6(25 downto 0);
  SHIFTOUTLdd7(1 downto 0) <= SHIFTOUTLdd6(27 downto 26);
 
  SHIFTOUTRdd8(27 downto 2) <= SHIFTOUTRdd7(25 downto 0);
  SHIFTOUTRdd8(1 downto 0) <= SHIFTOUTRdd7(27 downto 26);
 
  SHIFTOUTLdd8(27 downto 2) <= SHIFTOUTLdd7(25 downto 0);
  SHIFTOUTLdd8(1 downto 0) <= SHIFTOUTLdd7(27 downto 26);
 
  SHIFTOUTRdd9(27 downto 1) <= SHIFTOUTRdd8(26 downto 0);
  SHIFTOUTRdd9(0) <= SHIFTOUTRdd8(27);
 
  SHIFTOUTLdd9(27 downto 1) <= SHIFTOUTLdd8(26 downto 0);
  SHIFTOUTLdd9(0) <= SHIFTOUTLdd8(27);
 
  SHIFTOUTRdd10(27 downto 2) <= SHIFTOUTRdd9(25 downto 0);
  SHIFTOUTRdd10(1 downto 0) <= SHIFTOUTRdd9(27 downto 26);
 
  SHIFTOUTLdd10(27 downto 2) <= SHIFTOUTLdd9(25 downto 0);
  SHIFTOUTLdd10(1 downto 0) <= SHIFTOUTLdd9(27 downto 26);
 
  QSHIFTdd11(55 downto 28) <= SHIFTOUTLdd11(27 downto 0);
  QSHIFTdd11(27 downto 0) <= SHIFTOUTRdd11(27 downto 0);
 
  QSHIFTdd12(55 downto 28) <= SHIFTOUTLdd12(27 downto 0);
  QSHIFTdd12(27 downto 0) <= SHIFTOUTRdd12(27 downto 0);
 
  QSHIFTdd13(55 downto 28) <= SHIFTOUTLdd13(27 downto 0);
  QSHIFTdd13(27 downto 0) <= SHIFTOUTRdd13(27 downto 0);
 
  QSHIFTdd14(55 downto 28) <= SHIFTOUTLdd14(27 downto 0);
  QSHIFTdd14(27 downto 0) <= SHIFTOUTRdd14(27 downto 0);
 
  QSHIFTdd15(55 downto 28) <= SHIFTOUTLdd15(27 downto 0);
  QSHIFTdd15(27 downto 0) <= SHIFTOUTRdd15(27 downto 0);
 
  QSHIFTdd16(55 downto 28) <= SHIFTOUTLdd16(27 downto 0);
  QSHIFTdd16(27 downto 0) <= SHIFTOUTRdd16(27 downto 0);
 
  SHIFTOUTRdd11(27 downto 2) <= SHIFTOUTRdd10(25 downto 0);
  SHIFTOUTRdd11(1 downto 0) <= SHIFTOUTRdd10(27 downto 26);
 
  SHIFTOUTLdd11(27 downto 2) <= SHIFTOUTLdd10(25 downto 0);
  SHIFTOUTLdd11(1 downto 0) <= SHIFTOUTLdd10(27 downto 26);
 
  SHIFTOUTRdd12(27 downto 2) <= SHIFTOUTRdd11(25 downto 0);
  SHIFTOUTRdd12(1 downto 0) <= SHIFTOUTRdd11(27 downto 26);
 
  SHIFTOUTLdd12(27 downto 2) <= SHIFTOUTLdd11(25 downto 0);
  SHIFTOUTLdd12(1 downto 0) <= SHIFTOUTLdd11(27 downto 26);
 
  SHIFTOUTRdd13(27 downto 2) <= SHIFTOUTRdd12(25 downto 0);
  SHIFTOUTRdd13(1 downto 0) <= SHIFTOUTRdd12(27 downto 26);
 
  SHIFTOUTLdd13(27 downto 2) <= SHIFTOUTLdd12(25 downto 0);
  SHIFTOUTLdd13(1 downto 0) <= SHIFTOUTLdd12(27 downto 26);
 
  SHIFTOUTRdd14(27 downto 2) <= SHIFTOUTRdd13(25 downto 0);
  SHIFTOUTRdd14(1 downto 0) <= SHIFTOUTRdd13(27 downto 26);
 
  SHIFTOUTLdd14(27 downto 2) <= SHIFTOUTLdd13(25 downto 0);
  SHIFTOUTLdd14(1 downto 0) <= SHIFTOUTLdd13(27 downto 26);
 
  SHIFTOUTRdd15(27 downto 2) <= SHIFTOUTRdd14(25 downto 0);
  SHIFTOUTRdd15(1 downto 0) <= SHIFTOUTRdd14(27 downto 26);
 
  SHIFTOUTLdd15(27 downto 2) <= SHIFTOUTLdd14(25 downto 0);
  SHIFTOUTLdd15(1 downto 0) <= SHIFTOUTLdd14(27 downto 26);
 
  SHIFTOUTRdd16(27 downto 1) <= SHIFTOUTRdd15(26 downto 0);
  SHIFTOUTRdd16(0) <= SHIFTOUTRdd15(27);
 
  SHIFTOUTLdd16(27 downto 1) <= SHIFTOUTLdd15(26 downto 0);
  SHIFTOUTLdd16(0) <= SHIFTOUTLdd15(27);
end SUB_KEY;
----------------------------------------------------
--  
--  Library Name :  DES3
--  Unit    Name :  CTRL_ES
--  Unit    Type :  State Machine
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_UNSIGNED.all;
entity CTRL_ES is
  port (
        RST : in std_logic;
        CLK : in std_logic;
        E : in std_logic;
        E_D : in std_logic;
        mux_s0 : out std_logic;
        mux_s1 : out std_logic_vector(1 downto 0 );
        mux_s2 : out std_logic_vector(1 downto 0 );
        mux_s3 : out std_logic;
        MUX_E1 : out std_logic_vector(3 downto 0 );
        BUSY : out std_logic;
        OV : out std_logic
        );
 
end CTRL_ES;
 
 
architecture CTRL_ES of CTRL_ES is
 
  signal MUX_E1_S : std_logic_vector(3 downto 0 );
 
  type visual_S0_states is (S0, S1, S18, S2, S3, S4, S5, S6, S7, S8, S9);
  signal visual_S0_current : visual_S0_states;
 
 
  type visual_S10_states is (S10, S11, S12, S13, S14, S15, S16);
  signal visual_S10_current : visual_S10_states;
 
 
begin
 
 
 
  -- Synchronous process
  CTRL_ES_S0:
  process (CLK, RST)
    variable i : INTEGER;
    variable s : INTEGER;
  begin
 
    if (RST = '0') then
      mux_s0<='1';mux_s1<="00";
      mux_s3<='0';mux_s2<="00";
      i:=0;BUSY<='0';OV<='0';
      visual_S0_current <= S0;
    elsif (CLK'event and CLK = '1') then
 
      case visual_S0_current is
        when S0 =>
          if (E = '1') then
            mux_s0<='0';mux_s1<="00";
            mux_s3<='0';mux_s2<="10";
            i:=0;BUSY<='1';
            visual_S0_current <= S1;
          else
            visual_S0_current <= S0;
          end if;
 
        when S1 =>
          mux_s0<='1';
          mux_s1<="10";
          visual_S0_current <= S7;
 
        when S18 =>
          mux_s0<='1';mux_s1<="00";
          mux_s3<='0';mux_s2<="00";
          i:=0;BUSY<='0';OV<='0';
          visual_S0_current <= S0;
 
        when S2 =>
          if (i < 13) then
            i:=i+1;
            visual_S0_current <= S2;
          elsif (i = 13) then
            mux_s0<='0';mux_s1<="00";
            mux_s3<='1';
            i:=0;
            visual_S0_current <= S3;
          else
            visual_S0_current <= S2;
          end if;
 
        when S3 =>
          mux_s0<='1';mux_s2<="11";
          mux_s1<="10";
          visual_S0_current <= S8;
 
        when S4 =>
          if (i = 13) then
            mux_s0<='0';mux_s1<="00";
            mux_s3<='0';mux_s2<="00";
            i:=0;
            visual_S0_current <= S5;
          elsif (i < 13) then
            i:=i+1;
            visual_S0_current <= S4;
          else
            visual_S0_current <= S4;
          end if;
 
        when S5 =>
          mux_s0<='1';mux_s2<="11";
          mux_s1<="10";
          visual_S0_current <= S9;
 
        when S6 =>
          if (i = 13) then
            OV<='1';
            visual_S0_current <= S18;
          else
            i:=i+1;
            visual_S0_current <= S6;
          end if;
 
        when S7 =>
          mux_s1<="01";
          mux_s2<="00";
          visual_S0_current <= S2;
 
        when S8 =>
          mux_s1<="01";
          visual_S0_current <= S4;
 
        when S9 =>
          mux_s0<='1';mux_s1<="01";
          visual_S0_current <= S6;
 
        when others =>
 
          mux_s0<='1';mux_s1<="00";
          mux_s3<='0';mux_s2<="00";
          i:=0;BUSY<='0';OV<='0';
          visual_S0_current <= S0;
      end case;
    end if;
  end process;
 
 
 
  -- Synchronous process
  CTRL_ES_S10:
  process (CLK, RST)
    variable s : INTEGER;
  begin
 
    if (RST = '0') then
      MUX_E1_S<="0000";
      s:=0;
      visual_S10_current <= S10;
    elsif (CLK'event and CLK = '1') then
 
      case visual_S10_current is
        when S10 =>
          if (E = '1' and E_D = '0') then
            visual_S10_current <= S11;
          elsif (E = '1' and E_D = '1') then
            MUX_E1_S<="1111";
            visual_S10_current <= S14;
          else
            visual_S10_current <= S10;
          end if;
 
        when S11 =>
          if (s < 15) then
            MUX_E1_S<=MUX_E1_S+1;
            s:=s+1;
            visual_S10_current <= S11;
          elsif (s = 15) then
            visual_S10_current <= S12;
          else
            visual_S10_current <= S11;
          end if;
 
        when S12 =>
          if (s < 30) then
            MUX_E1_S<=MUX_E1_S-1;
            s:=s+1;
            visual_S10_current <= S12;
          elsif (s = 30) then
            visual_S10_current <= S13;
          else
            visual_S10_current <= S12;
          end if;
 
        when S13 =>
          if (E = '1' and E_D = '0') then
            MUX_E1_S<="0000";
            s:=0;
            visual_S10_current <= S11;
          elsif (s < 45) then
            MUX_E1_S<=MUX_E1_S+1;
            s:=s+1;
            visual_S10_current <= S13;
          else
            MUX_E1_S<="0000";
            s:=0;
            visual_S10_current <= S10;
          end if;
 
        when S14 =>
          if (s < 15) then
            MUX_E1_S<=MUX_E1_S-1;
            s:=s+1;
            visual_S10_current <= S14;
          elsif (s = 15) then
            visual_S10_current <= S15;
          else
            visual_S10_current <= S14;
          end if;
 
        when S15 =>
          if (s < 30) then
            MUX_E1_S<=MUX_E1_S+1;
            s:=s+1;
            visual_S10_current <= S15;
          elsif (s = 30) then
            visual_S10_current <= S16;
          else
            visual_S10_current <= S15;
          end if;
 
        when S16 =>
          if (E = '1' and E_D = '1') then
            MUX_E1_S<="1111";
            s:=0;
            visual_S10_current <= S14;
          elsif (s < 45) then
            MUX_E1_S<=MUX_E1_S-1;
            s:=s+1;
            visual_S10_current <= S16;
          else
            MUX_E1_S<="0000";
            s:=0;
            visual_S10_current <= S10;
          end if;
 
        when others =>
 
          MUX_E1_S<="0000";
          s:=0;
          visual_S10_current <= S10;
      end case;
    end if;
  end process;
 
 
  MUX_E1<=MUX_E1_S;
end CTRL_ES;
----------------------------------------------------
--  
--  Library Name :  DES3
--  Unit    Name :  PMT64_64_E
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_1164.all;
entity PMT64_64_E is
  port (
        D : in std_logic_vector(63 downto 0 );
        Q : out std_logic_vector(63 downto 0 )
        );
 
 
end PMT64_64_E;
 
 
architecture PMT64_64_E of PMT64_64_E is
 
  signal Se0 : std_logic;
  signal Se1 : std_logic;
  signal Se10 : std_logic;
  signal Se11 : std_logic;
  signal Se12 : std_logic;
  signal Se13 : std_logic;
  signal Se14 : std_logic;
  signal Se15 : std_logic;
  signal Se16 : std_logic;
  signal Se17 : std_logic;
  signal Se18 : std_logic;
  signal Se19 : std_logic;
  signal Se2 : std_logic;
  signal Se20 : std_logic;
  signal Se21 : std_logic;
  signal Se22 : std_logic;
  signal Se23 : std_logic;
  signal Se24 : std_logic;
  signal Se25 : std_logic;
  signal Se26 : std_logic;
  signal Se27 : std_logic;
  signal Se28 : std_logic;
  signal Se29 : std_logic;
  signal Se3 : std_logic;
  signal Se30 : std_logic;
  signal Se31 : std_logic;
  signal Se32 : std_logic;
  signal Se33 : std_logic;
  signal Se34 : std_logic;
  signal Se35 : std_logic;
  signal Se36 : std_logic;
  signal Se37 : std_logic;
  signal Se38 : std_logic;
  signal Se39 : std_logic;
  signal Se4 : std_logic;
  signal Se40 : std_logic;
  signal Se41 : std_logic;
  signal Se42 : std_logic;
  signal Se43 : std_logic;
  signal Se44 : std_logic;
  signal Se45 : std_logic;
  signal Se46 : std_logic;
  signal Se47 : std_logic;
  signal Se48 : std_logic;
  signal Se49 : std_logic;
  signal Se5 : std_logic;
  signal Se50 : std_logic;
  signal Se51 : std_logic;
  signal Se52 : std_logic;
  signal Se53 : std_logic;
  signal Se54 : std_logic;
  signal Se55 : std_logic;
  signal Se56 : std_logic;
  signal Se57 : std_logic;
  signal Se58 : std_logic;
  signal Se59 : std_logic;
  signal Se6 : std_logic;
  signal Se60 : std_logic;
  signal Se61 : std_logic;
  signal Se62 : std_logic;
  signal Se63 : std_logic;
  signal Se7 : std_logic;
  signal Se8 : std_logic;
  signal Se9 : std_logic;
 
 
begin
 
  Se32 <= D(32);
  Se33 <= D(33);
  Se34 <= D(34);
  Se35 <= D(35);
  Se36 <= D(36);
  Se37 <= D(37);
  Se38 <= D(38);
  Se39 <= D(39);
  Se40 <= D(40);
  Se41 <= D(41);
  Se42 <= D(42);
  Se43 <= D(43);
  Se44 <= D(44);
  Se45 <= D(45);
  Se46 <= D(46);
  Se47 <= D(47);
  Se48 <= D(48);
  Se49 <= D(49);
  Se50 <= D(50);
  Se51 <= D(51);
  Se52 <= D(52);
  Se53 <= D(53);
  Se54 <= D(54);
  Se55 <= D(55);
  Se56 <= D(56);
  Se57 <= D(57);
  Se58 <= D(58);
  Se59 <= D(59);
  Se60 <= D(60);
  Se61 <= D(61);
  Se62 <= D(62);
  Se63 <= D(63);
 
  Se0 <= D(0);
  Se1 <= D(1);
  Se2 <= D(2);
  Se3 <= D(3);
  Se4 <= D(4);
  Se5 <= D(5);
  Se6 <= D(6);
  Se7 <= D(7);
  Se8 <= D(8);
  Se9 <= D(9);
  Se10 <= D(10);