des3_top.vhd

3des10m性能优化设计代码

----------------------------------------------------
--  
--  Library Name :  DES3
--  Unit    Name :  PMT56_48_M2
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
entity PMT56_48_M2 is
  port (
        D : in std_logic_vector(55 downto 0 );
        Q : out std_logic_vector(47 downto 0 )
        );
 
 
end PMT56_48_M2;
 
 
architecture PMT56_48_M2 of PMT56_48_M2 is
 
  signal Sy0 : std_logic;
  signal Sy1 : std_logic;
  signal Sy10 : std_logic;
  signal Sy11 : std_logic;
  signal Sy12 : std_logic;
  signal Sy13 : std_logic;
  signal Sy14 : std_logic;
  signal Sy15 : std_logic;
  signal Sy16 : std_logic;
  signal Sy17 : std_logic;
  signal Sy18 : std_logic;
  signal Sy19 : std_logic;
  signal Sy2 : std_logic;
  signal Sy20 : std_logic;
  signal Sy21 : std_logic;
  signal Sy22 : std_logic;
  signal Sy23 : std_logic;
  signal Sy24 : std_logic;
  signal Sy25 : std_logic;
  signal Sy26 : std_logic;
  signal Sy27 : std_logic;
  signal Sy28 : std_logic;
  signal Sy29 : std_logic;
  signal Sy3 : std_logic;
  signal Sy30 : std_logic;
  signal Sy31 : std_logic;
  signal Sy32 : std_logic;
  signal Sy33 : std_logic;
  signal Sy34 : std_logic;
  signal Sy35 : std_logic;
  signal Sy36 : std_logic;
  signal Sy37 : std_logic;
  signal Sy38 : std_logic;
  signal Sy39 : std_logic;
  signal Sy4 : std_logic;
  signal Sy40 : std_logic;
  signal Sy41 : std_logic;
  signal Sy42 : std_logic;
  signal Sy43 : std_logic;
  signal Sy44 : std_logic;
  signal Sy45 : std_logic;
  signal Sy46 : std_logic;
  signal Sy47 : std_logic;
  signal Sy48 : std_logic;
  signal Sy49 : std_logic;
  signal Sy5 : std_logic;
  signal Sy50 : std_logic;
  signal Sy51 : std_logic;
  signal Sy52 : std_logic;
  signal Sy53 : std_logic;
  signal Sy54 : std_logic;
  signal Sy55 : std_logic;
  signal Sy6 : std_logic;
  signal Sy7 : std_logic;
  signal Sy8 : std_logic;
  signal Sy9 : std_logic;
 
 
begin
 
  Sy5 <= D(50);
  Sy14 <= D(41);
  Sy4 <= D(51);
  Sy23 <= D(32);
  Sy16 <= D(39);
  Sy9 <= D(46);
  Sy2 <= D(53);
  Sy7 <= D(48);
  Sy13 <= D(42);
  Sy17 <= D(38);
  Sy1 <= D(54);
  Sy40 <= D(15);
  Sy27 <= D(28);
  Sy44 <= D(11);
  Sy35 <= D(20);
  Sy37 <= D(18);
  Sy46 <= D(9);
  Sy29 <= D(26);
  Sy39 <= D(16);
  Sy33 <= D(22);
  Sy45 <= D(10);
  Sy36 <= D(19);
  Sy38 <= D(17);
  Sy42 <= D(13);
  Sy32 <= D(23);
  Sy41 <= D(14);
  Sy24 <= D(31);
  Sy43 <= D(12);
  Sy19 <= D(36);
  Sy12 <= D(43);
  Sy28 <= D(27);
  Sy30 <= D(25);
  Sy25 <= D(30);
  Sy47 <= D(8);
  Sy34 <= D(21);
  Sy26 <= D(29);
  Sy31 <= D(24);
  Sy21 <= D(34);
  Sy0 <= D(55);
  Sy20 <= D(35);
  Sy11 <= D(44);
  Sy10 <= D(45);
  Sy3 <= D(52);
  Sy6 <= D(49);
  Sy18 <= D(37);
  Sy8 <= D(47);
  Sy15 <= D(40);
  Sy22 <= D(33);
  Sy48 <= D(7);
  Sy52 <= D(3);
  Sy54 <= D(1);
  Sy53 <= D(2);
  Sy50 <= D(5);
  Sy49 <= D(6);
  Sy51 <= D(4);
  Sy55 <= D(0);
 
  Q(47) <= Sy13;
  Q(46) <= Sy16;
  Q(45) <= Sy10;
  Q(44) <= Sy23;
  Q(43) <= Sy0;
  Q(42) <= Sy4;
  Q(41) <= Sy2;
  Q(40) <= Sy27;
  Q(39) <= Sy14;
  Q(38) <= Sy5;
  Q(37) <= Sy20;
  Q(36) <= Sy9;
  Q(35) <= Sy22;
  Q(34) <= Sy18;
  Q(33) <= Sy11;
  Q(32) <= Sy3;
  Q(31) <= Sy25;
  Q(30) <= Sy7;
  Q(29) <= Sy15;
  Q(28) <= Sy6;
  Q(27) <= Sy26;
  Q(26) <= Sy19;
  Q(25) <= Sy12;
  Q(24) <= Sy1;
  Q(23) <= Sy40;
  Q(22) <= Sy51;
  Q(21) <= Sy30;
  Q(20) <= Sy36;
  Q(19) <= Sy46;
  Q(18) <= Sy54;
  Q(17) <= Sy29;
  Q(16) <= Sy39;
  Q(15) <= Sy50;
  Q(14) <= Sy44;
  Q(13) <= Sy32;
  Q(12) <= Sy47;
  Q(11) <= Sy43;
  Q(10) <= Sy48;
  Q(9) <= Sy38;
  Q(8) <= Sy55;
  Q(7) <= Sy33;
  Q(6) <= Sy52;
  Q(5) <= Sy45;
  Q(4) <= Sy41;
  Q(3) <= Sy49;
  Q(2) <= Sy35;
  Q(1) <= Sy28;
  Q(0) <= Sy31;
end PMT56_48_M2;
----------------------------------------------------
--  
--  Library Name :  DES3
--  Unit    Name :  SUB_KEY
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 
library ieee;
use ieee.STD_LOGIC_1164.all;
library std;
use std.STANDARD.all;
entity SUB_KEY is
  port (
        Kt : in std_logic_vector(63 downto 0 );
        SUB_K1 : out std_logic_vector(47 downto 0 );
        SUB_K10 : out std_logic_vector(47 downto 0 );
        SUB_K11 : out std_logic_vector(47 downto 0 );
        SUB_K12 : out std_logic_vector(47 downto 0 );
        SUB_K13 : out std_logic_vector(47 downto 0 );
        SUB_K14 : out std_logic_vector(47 downto 0 );
        SUB_K15 : out std_logic_vector(47 downto 0 );
        SUB_K16 : out std_logic_vector(47 downto 0 );
        SUB_K2 : out std_logic_vector(47 downto 0 );
        SUB_K3 : out std_logic_vector(47 downto 0 );
        SUB_K4 : out std_logic_vector(47 downto 0 );
        SUB_K5 : out std_logic_vector(47 downto 0 );
        SUB_K6 : out std_logic_vector(47 downto 0 );
        SUB_K7 : out std_logic_vector(47 downto 0 );
        SUB_K8 : out std_logic_vector(47 downto 0 );
        SUB_K9 : out std_logic_vector(47 downto 0 )
        );
 
 
end SUB_KEY;
 
 
use work.all;
architecture SUB_KEY of SUB_KEY is
 
  signal QSHIFTdd1 : std_logic_vector(55 downto 0 );
  signal QSHIFTdd10 : std_logic_vector(55 downto 0 );
  signal QSHIFTdd11 : std_logic_vector(55 downto 0 );
  signal QSHIFTdd12 : std_logic_vector(55 downto 0 );
  signal QSHIFTdd13 : std_logic_vector(55 downto 0 );
  signal QSHIFTdd14 : std_logic_vector(55 downto 0 );
  signal QSHIFTdd15 : std_logic_vector(55 downto 0 );
  signal QSHIFTdd16 : std_logic_vector(55 downto 0 );
  signal QSHIFTdd2 : std_logic_vector(55 downto 0 );
  signal QSHIFTdd3 : std_logic_vector(55 downto 0 );
  signal QSHIFTdd4 : std_logic_vector(55 downto 0 );
  signal QSHIFTdd5 : std_logic_vector(55 downto 0 );
  signal QSHIFTdd6 : std_logic_vector(55 downto 0 );
  signal QSHIFTdd7 : std_logic_vector(55 downto 0 );
  signal QSHIFTdd8 : std_logic_vector(55 downto 0 );
  signal QSHIFTdd9 : std_logic_vector(55 downto 0 );
  signal SHIFTOUTLdd1 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTLdd10 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTLdd11 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTLdd12 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTLdd13 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTLdd14 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTLdd15 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTLdd16 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTLdd2 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTLdd3 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTLdd4 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTLdd5 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTLdd6 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTLdd7 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTLdd8 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTLdd9 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTRdd1 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTRdd10 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTRdd11 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTRdd12 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTRdd13 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTRdd14 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTRdd15 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTRdd16 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTRdd2 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTRdd3 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTRdd4 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTRdd5 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTRdd6 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTRdd7 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTRdd8 : std_logic_vector(27 downto 0 );
  signal SHIFTOUTRdd9 : std_logic_vector(27 downto 0 );
  signal smm0 : std_logic;
  signal smm1 : std_logic;
  signal smm10 : std_logic;
  signal smm11 : std_logic;
  signal smm12 : std_logic;
  signal smm13 : std_logic;
  signal smm14 : std_logic;
  signal smm15 : std_logic;
  signal smm16 : std_logic;
  signal smm17 : std_logic;
  signal smm18 : std_logic;
  signal smm19 : std_logic;
  signal smm2 : std_logic;
  signal smm20 : std_logic;
  signal smm21 : std_logic;
  signal smm22 : std_logic;
  signal smm23 : std_logic;
  signal smm24 : std_logic;
  signal smm25 : std_logic;
  signal smm26 : std_logic;
  signal smm27 : std_logic;
  signal smm28 : std_logic;
  signal smm29 : std_logic;
  signal smm3 : std_logic;
  signal smm30 : std_logic;
  signal smm31 : std_logic;
  signal smm32 : std_logic;
  signal smm33 : std_logic;
  signal smm34 : std_logic;
  signal smm35 : std_logic;
  signal smm36 : std_logic;
  signal smm37 : std_logic;
  signal smm38 : std_logic;
  signal smm39 : std_logic;
  signal smm4 : std_logic;
  signal smm40 : std_logic;
  signal smm41 : std_logic;
  signal smm42 : std_logic;
  signal smm43 : std_logic;
  signal smm44 : std_logic;
  signal smm45 : std_logic;
  signal smm46 : std_logic;
  signal smm47 : std_logic;
  signal smm48 : std_logic;
  signal smm49 : std_logic;
  signal smm5 : std_logic;
  signal smm50 : std_logic;
  signal smm51 : std_logic;
  signal smm52 : std_logic;
  signal smm53 : std_logic;
  signal smm54 : std_logic;
  signal smm55 : std_logic;
  signal smm56 : std_logic;
  signal smm57 : std_logic;
  signal smm58 : std_logic;
  signal smm59 : std_logic;
  signal smm6 : std_logic;
  signal smm60 : std_logic;
  signal smm61 : std_logic;
  signal smm62 : std_logic;
  signal smm63 : std_logic;
  signal smm7 : std_logic;
  signal smm8 : std_logic;
  signal smm9 : std_logic;
  signal Spp7 : std_logic_vector(55 downto 0 );
  component PMT56_48_M2
      port (
            D : in std_logic_vector(55 downto 0 );
            Q : out std_logic_vector(47 downto 0 )
            );
  end component;
 
  -- Start Configuration Specification
  -- ++ for all : PMT56_48_M2 use entity work.PMT56_48_M2(PMT56_48_M2);
  -- End Configuration Specification
 
begin
 
  CP2: PMT56_48_M2
    port map (
              D => QSHIFTdd2(55 downto 0),
              Q => SUB_K2(47 downto 0)
              );
 
  CP3: PMT56_48_M2
    port map (
              D => QSHIFTdd3(55 downto 0),
              Q => SUB_K3(47 downto 0)
              );
 
  CP4: PMT56_48_M2
    port map (
              D => QSHIFTdd4(55 downto 0),
              Q => SUB_K4(47 downto 0)
              );
 
  CP5: PMT56_48_M2
    port map (
              D => QSHIFTdd5(55 downto 0),
              Q => SUB_K5(47 downto 0)
              );
 
  CP6: PMT56_48_M2
    port map (
              D => QSHIFTdd6(55 downto 0),
              Q => SUB_K6(47 downto 0)
              );
 
  CP7: PMT56_48_M2
    port map (
              D => QSHIFTdd7(55 downto 0),
              Q => SUB_K7(47 downto 0)
              );
 
  CP8: PMT56_48_M2
    port map (
              D => QSHIFTdd8(55 downto 0),
              Q => SUB_K8(47 downto 0)
              );
 
  CP9: PMT56_48_M2
    port map (
              D => QSHIFTdd9(55 downto 0),
              Q => SUB_K9(47 downto 0)
              );
 
  CP10: PMT56_48_M2
    port map (
              D => QSHIFTdd10(55 downto 0),
              Q => SUB_K10(47 downto 0)
              );
 
  CP11: PMT56_48_M2
    port map (
              D => QSHIFTdd11(55 downto 0),
              Q => SUB_K11(47 downto 0)
              );
 
  CP12: PMT56_48_M2
    port map (
              D => QSHIFTdd12(55 downto 0),
              Q => SUB_K12(47 downto 0)
              );
 
  CP13: PMT56_48_M2
    port map (
              D => QSHIFTdd13(55 downto 0),
              Q => SUB_K13(47 downto 0)
              );
 
  CP14: PMT56_48_M2
    port map (
              D => QSHIFTdd14(55 downto 0),
              Q => SUB_K14(47 downto 0)
              );
 
  CP15: PMT56_48_M2
    port map (
              D => QSHIFTdd15(55 downto 0),
              Q => SUB_K15(47 downto 0)
              );
 
  CP16: PMT56_48_M2
    port map (
              D => QSHIFTdd16(55 downto 0),
              Q => SUB_K16(47 downto 0)
              );
 
  CP1: PMT56_48_M2
    port map (
              D => QSHIFTdd1(55 downto 0),
              Q => SUB_K1(47 downto 0)
              );
 
  Spp7(55) <= smm56;
  Spp7(54) <= smm48;
  Spp7(53) <= smm40;
  Spp7(52) <= smm32;
  Spp7(51) <= smm24;
  Spp7(50) <= smm16;
  Spp7(49) <= smm8;
  Spp7(48) <= smm0;
  Spp7(47) <= smm57;
  Spp7(46) <= smm49;
  Spp7(45) <= smm41;
  Spp7(44) <= smm33;
  Spp7(43) <= smm25;
  Spp7(42) <= smm17;
  Spp7(41) <= smm9;
  Spp7(40) <= smm1;
  Spp7(39) <= smm58;
  Spp7(38) <= smm50;
  Spp7(37) <= smm42;
  Spp7(36) <= smm34;
  Spp7(35) <= smm26;
  Spp7(34) <= smm18;
  Spp7(33) <= smm10;
  Spp7(32) <= smm2;
  Spp7(31) <= smm59;
  Spp7(30) <= smm51;
  Spp7(29) <= smm43;
  Spp7(28) <= smm35;
  Spp7(27) <= smm62;
  Spp7(26) <= smm54;
  Spp7(25) <= smm46;
  Spp7(24) <= smm38;
  Spp7(23) <= smm30;
  Spp7(22) <= smm22;
  Spp7(21) <= smm14;
  Spp7(20) <= smm6;
  Spp7(19) <= smm61;
  Spp7(18) <= smm53;
  Spp7(17) <= smm45;
  Spp7(16) <= smm37;
  Spp7(15) <= smm29;
  Spp7(14) <= smm21;
  Spp7(13) <= smm13;
  Spp7(12) <= smm5;
  Spp7(11) <= smm60;
  Spp7(10) <= smm52;
  Spp7(9) <= smm44;
  Spp7(8) <= smm36;
  Spp7(7) <= smm28;
  Spp7(6) <= smm20;
  Spp7(5) <= smm12;
  Spp7(4) <= smm4;
  Spp7(3) <= smm27;
  Spp7(2) <= smm19;
  Spp7(1) <= smm11;
  Spp7(0) <= smm3;
 
  smm0 <= Kt(63);
  smm1 <= Kt(62);
  smm2 <= Kt(61);
  smm3 <= Kt(60);
  smm4 <= Kt(59);
  smm7 <= Kt(56);
  smm6 <= Kt(57);
  smm5 <= Kt(58);
  smm8 <= Kt(55);
  smm11 <= Kt(52);
  smm10 <= Kt(53);
  smm9 <= Kt(54);
  smm12 <= Kt(51);
  smm15 <= Kt(48);
  smm14 <= Kt(49);
  smm13 <= Kt(50);
  smm16 <= Kt(47);
  smm29 <= Kt(34);
  smm30 <= Kt(33);
  smm31 <= Kt(32);
  smm28 <= Kt(35);
  smm25 <= Kt(38);
  smm26 <= Kt(37);
  smm27 <= Kt(36);
  smm24 <= Kt(39);
  smm21 <= Kt(42);
  smm22 <= Kt(41);
  smm23 <= Kt(40);
  smm20 <= Kt(43);
  smm19 <= Kt(44);
  smm18 <= Kt(45);
  smm17 <= Kt(46);
 
  smm32 <= Kt(31);
  smm45 <= Kt(18);
  smm46 <= Kt(17);
  smm47 <= Kt(16);
  smm44 <= Kt(19);
  smm41 <= Kt(22);
  smm42 <= Kt(21);
  smm43 <= Kt(20);
  smm40 <= Kt(23);
  smm37 <= Kt(26);
  smm38 <= Kt(25);
  smm39 <= Kt(24);
  smm36 <= Kt(27);
  smm35 <= Kt(28);
  smm34 <= Kt(29);
  smm33 <= Kt(30);
  smm48 <= Kt(15);