train.hif

基于FPGA火车状态机的实现方法

Version 9.0 Build 132 02/25/2009 SJ Full Version
11
1040
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
debounce
# storage
db|train.(1).cnf
db|train.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
debounce.vhd
e1c84e8cf7dc738535d1f3b8ce6a69
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# lmf
c:|altera|90|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
train
# storage
db|train.(0).cnf
db|train.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
train.v
3517ad15a8f848ed2473f2ca64f477
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
ABout
0
PARAMETER_SIGNED_DEC
DEF
Ain
1
PARAMETER_SIGNED_DEC
DEF
Bin
2
PARAMETER_SIGNED_DEC
DEF
Astop
3
PARAMETER_SIGNED_DEC
DEF
Bstop
4
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
|
}
# macro_sequence

# end
# complete