prev_cmp_train.tan.qmsg

基于FPGA火车状态机的实现方法

{ "Info" "ITDB_TH_RESULT" "state.Bstop sensor2 clock -3.227 ns register " "Info: th for register \"state.Bstop\" (data pin = \"sensor2\", clock pin = \"clock\") is -3.227 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.680 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.680 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns clock 1 CLK PIN_U30 5 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_U30; Fanout = 5; CLK Node = 'clock'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.291 ns) + CELL(0.537 ns) 2.680 ns state.Bstop 2 REG LCFF_X94_Y15_N23 3 " "Info: 2: + IC(1.291 ns) + CELL(0.537 ns) = 2.680 ns; Loc. = LCFF_X94_Y15_N23; Fanout = 3; REG Node = 'state.Bstop'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.828 ns" { clock state.Bstop } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.389 ns ( 51.83 % ) " "Info: Total cell delay = 1.389 ns ( 51.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.291 ns ( 48.17 % ) " "Info: Total interconnect delay = 1.291 ns ( 48.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.680 ns" { clock state.Bstop } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.680 ns" { clock {} clock~combout {} state.Bstop {} } { 0.000ns 0.000ns 1.291ns } { 0.000ns 0.852ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "train.v" "" { Text "E:/exercises/train_4/train.v" 12 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.173 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.173 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.832 ns) 0.832 ns sensor2 1 PIN PIN_AB26 4 " "Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_AB26; Fanout = 4; PIN Node = 'sensor2'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { sensor2 } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.107 ns) + CELL(0.150 ns) 6.089 ns Selector4~1 2 COMB LCCOMB_X94_Y15_N22 1 " "Info: 2: + IC(5.107 ns) + CELL(0.150 ns) = 6.089 ns; Loc. = LCCOMB_X94_Y15_N22; Fanout = 1; COMB Node = 'Selector4~1'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.257 ns" { sensor2 Selector4~1 } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.173 ns state.Bstop 3 REG LCFF_X94_Y15_N23 3 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.173 ns; Loc. = LCFF_X94_Y15_N23; Fanout = 3; REG Node = 'state.Bstop'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { Selector4~1 state.Bstop } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.066 ns ( 17.27 % ) " "Info: Total cell delay = 1.066 ns ( 17.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.107 ns ( 82.73 % ) " "Info: Total interconnect delay = 5.107 ns ( 82.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.173 ns" { sensor2 Selector4~1 state.Bstop } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.173 ns" { sensor2 {} sensor2~combout {} Selector4~1 {} state.Bstop {} } { 0.000ns 0.000ns 5.107ns 0.000ns } { 0.000ns 0.832ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.680 ns" { clock state.Bstop } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.680 ns" { clock {} clock~combout {} state.Bstop {} } { 0.000ns 0.000ns 1.291ns } { 0.000ns 0.852ns 0.537ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.173 ns" { sensor2 Selector4~1 state.Bstop } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.173 ns" { sensor2 {} sensor2~combout {} Selector4~1 {} state.Bstop {} } { 0.000ns 0.000ns 5.107ns 0.000ns } { 0.000ns 0.832ns 0.150ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "139 " "Info: Peak virtual memory: 139 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 10 12:36:57 2012 " "Info: Processing ended: Tue Jul 10 12:36:57 2012" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}