prev_cmp_train.tan.qmsg

基于FPGA火车状态机的实现方法

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "train.v" "" { Text "E:/exercises/train_4/train.v" 6 -1 0 } } { "c:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clock register register state.Bin state.Bin 450.05 MHz Internal " "Info: Clock \"clock\" Internal fmax is restricted to 450.05 MHz between source register \"state.Bin\" and destination register \"state.Bin\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.222 ns " "Info: fmax restricted to clock pin edge rate 2.222 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.165 ns + Longest register register " "Info: + Longest register to register delay is 1.165 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state.Bin 1 REG LCFF_X94_Y15_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X94_Y15_N9; Fanout = 4; REG Node = 'state.Bin'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { state.Bin } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.537 ns) + CELL(0.150 ns) 0.687 ns Selector2~0 2 COMB LCCOMB_X94_Y15_N2 1 " "Info: 2: + IC(0.537 ns) + CELL(0.150 ns) = 0.687 ns; Loc. = LCCOMB_X94_Y15_N2; Fanout = 1; COMB Node = 'Selector2~0'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.687 ns" { state.Bin Selector2~0 } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.244 ns) + CELL(0.150 ns) 1.081 ns Selector2~1 3 COMB LCCOMB_X94_Y15_N8 1 " "Info: 3: + IC(0.244 ns) + CELL(0.150 ns) = 1.081 ns; Loc. = LCCOMB_X94_Y15_N8; Fanout = 1; COMB Node = 'Selector2~1'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { Selector2~0 Selector2~1 } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.165 ns state.Bin 4 REG LCFF_X94_Y15_N9 4 " "Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 1.165 ns; Loc. = LCFF_X94_Y15_N9; Fanout = 4; REG Node = 'state.Bin'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { Selector2~1 state.Bin } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.384 ns ( 32.96 % ) " "Info: Total cell delay = 0.384 ns ( 32.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.781 ns ( 67.04 % ) " "Info: Total interconnect delay = 0.781 ns ( 67.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.165 ns" { state.Bin Selector2~0 Selector2~1 state.Bin } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "1.165 ns" { state.Bin {} Selector2~0 {} Selector2~1 {} state.Bin {} } { 0.000ns 0.537ns 0.244ns 0.000ns } { 0.000ns 0.150ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.680 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.680 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns clock 1 CLK PIN_U30 5 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_U30; Fanout = 5; CLK Node = 'clock'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.291 ns) + CELL(0.537 ns) 2.680 ns state.Bin 2 REG LCFF_X94_Y15_N9 4 " "Info: 2: + IC(1.291 ns) + CELL(0.537 ns) = 2.680 ns; Loc. = LCFF_X94_Y15_N9; Fanout = 4; REG Node = 'state.Bin'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.828 ns" { clock state.Bin } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.389 ns ( 51.83 % ) " "Info: Total cell delay = 1.389 ns ( 51.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.291 ns ( 48.17 % ) " "Info: Total interconnect delay = 1.291 ns ( 48.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.680 ns" { clock state.Bin } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.680 ns" { clock {} clock~combout {} state.Bin {} } { 0.000ns 0.000ns 1.291ns } { 0.000ns 0.852ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.680 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.680 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns clock 1 CLK PIN_U30 5 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_U30; Fanout = 5; CLK Node = 'clock'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.291 ns) + CELL(0.537 ns) 2.680 ns state.Bin 2 REG LCFF_X94_Y15_N9 4 " "Info: 2: + IC(1.291 ns) + CELL(0.537 ns) = 2.680 ns; Loc. = LCFF_X94_Y15_N9; Fanout = 4; REG Node = 'state.Bin'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.828 ns" { clock state.Bin } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.389 ns ( 51.83 % ) " "Info: Total cell delay = 1.389 ns ( 51.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.291 ns ( 48.17 % ) " "Info: Total interconnect delay = 1.291 ns ( 48.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.680 ns" { clock state.Bin } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.680 ns" { clock {} clock~combout {} state.Bin {} } { 0.000ns 0.000ns 1.291ns } { 0.000ns 0.852ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.680 ns" { clock state.Bin } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.680 ns" { clock {} clock~combout {} state.Bin {} } { 0.000ns 0.000ns 1.291ns } { 0.000ns 0.852ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "train.v" "" { Text "E:/exercises/train_4/train.v" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "train.v" "" { Text "E:/exercises/train_4/train.v" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.165 ns" { state.Bin Selector2~0 Selector2~1 state.Bin } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "1.165 ns" { state.Bin {} Selector2~0 {} Selector2~1 {} state.Bin {} } { 0.000ns 0.537ns 0.244ns 0.000ns } { 0.000ns 0.150ns 0.150ns 0.084ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.680 ns" { clock state.Bin } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.680 ns" { clock {} clock~combout {} state.Bin {} } { 0.000ns 0.000ns 1.291ns } { 0.000ns 0.852ns 0.537ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { state.Bin } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { state.Bin {} } {  } {  } "" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 12 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_TSU_RESULT" "state.ABout sensor3 clock 4.315 ns register " "Info: tsu for register \"state.ABout\" (data pin = \"sensor3\", clock pin = \"clock\") is 4.315 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.031 ns + Longest pin register " "Info: + Longest pin to register delay is 7.031 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.832 ns) 0.832 ns sensor3 1 PIN PIN_AB25 4 " "Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_AB25; Fanout = 4; PIN Node = 'sensor3'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { sensor3 } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.305 ns) + CELL(0.419 ns) 6.556 ns Selector0~0 2 COMB LCCOMB_X94_Y15_N6 1 " "Info: 2: + IC(5.305 ns) + CELL(0.419 ns) = 6.556 ns; Loc. = LCCOMB_X94_Y15_N6; Fanout = 1; COMB Node = 'Selector0~0'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.724 ns" { sensor3 Selector0~0 } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.241 ns) + CELL(0.150 ns) 6.947 ns Selector0~1 3 COMB LCCOMB_X94_Y15_N16 1 " "Info: 3: + IC(0.241 ns) + CELL(0.150 ns) = 6.947 ns; Loc. = LCCOMB_X94_Y15_N16; Fanout = 1; COMB Node = 'Selector0~1'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.391 ns" { Selector0~0 Selector0~1 } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 7.031 ns state.ABout 4 REG LCFF_X94_Y15_N17 3 " "Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 7.031 ns; Loc. = LCFF_X94_Y15_N17; Fanout = 3; REG Node = 'state.ABout'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { Selector0~1 state.ABout } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.485 ns ( 21.12 % ) " "Info: Total cell delay = 1.485 ns ( 21.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.546 ns ( 78.88 % ) " "Info: Total interconnect delay = 5.546 ns ( 78.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "7.031 ns" { sensor3 Selector0~0 Selector0~1 state.ABout } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "7.031 ns" { sensor3 {} sensor3~combout {} Selector0~0 {} Selector0~1 {} state.ABout {} } { 0.000ns 0.000ns 5.305ns 0.241ns 0.000ns } { 0.000ns 0.832ns 0.419ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "train.v" "" { Text "E:/exercises/train_4/train.v" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.680 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 2.680 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns clock 1 CLK PIN_U30 5 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_U30; Fanout = 5; CLK Node = 'clock'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.291 ns) + CELL(0.537 ns) 2.680 ns state.ABout 2 REG LCFF_X94_Y15_N17 3 " "Info: 2: + IC(1.291 ns) + CELL(0.537 ns) = 2.680 ns; Loc. = LCFF_X94_Y15_N17; Fanout = 3; REG Node = 'state.ABout'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.828 ns" { clock state.ABout } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.389 ns ( 51.83 % ) " "Info: Total cell delay = 1.389 ns ( 51.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.291 ns ( 48.17 % ) " "Info: Total interconnect delay = 1.291 ns ( 48.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.680 ns" { clock state.ABout } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.680 ns" { clock {} clock~combout {} state.ABout {} } { 0.000ns 0.000ns 1.291ns } { 0.000ns 0.852ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "7.031 ns" { sensor3 Selector0~0 Selector0~1 state.ABout } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "7.031 ns" { sensor3 {} sensor3~combout {} Selector0~0 {} Selector0~1 {} state.ABout {} } { 0.000ns 0.000ns 5.305ns 0.241ns 0.000ns } { 0.000ns 0.832ns 0.419ns 0.150ns 0.084ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.680 ns" { clock state.ABout } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.680 ns" { clock {} clock~combout {} state.ABout {} } { 0.000ns 0.000ns 1.291ns } { 0.000ns 0.852ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock switch2 state.Astop 7.199 ns register " "Info: tco from clock \"clock\" to destination pin \"switch2\" through register \"state.Astop\" is 7.199 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.680 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 2.680 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns clock 1 CLK PIN_U30 5 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_U30; Fanout = 5; CLK Node = 'clock'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.291 ns) + CELL(0.537 ns) 2.680 ns state.Astop 2 REG LCFF_X94_Y15_N27 4 " "Info: 2: + IC(1.291 ns) + CELL(0.537 ns) = 2.680 ns; Loc. = LCFF_X94_Y15_N27; Fanout = 4; REG Node = 'state.Astop'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.828 ns" { clock state.Astop } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.389 ns ( 51.83 % ) " "Info: Total cell delay = 1.389 ns ( 51.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.291 ns ( 48.17 % ) " "Info: Total interconnect delay = 1.291 ns ( 48.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.680 ns" { clock state.Astop } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.680 ns" { clock {} clock~combout {} state.Astop {} } { 0.000ns 0.000ns 1.291ns } { 0.000ns 0.852ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "train.v" "" { Text "E:/exercises/train_4/train.v" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.269 ns + Longest register pin " "Info: + Longest register to pin delay is 4.269 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state.Astop 1 REG LCFF_X94_Y15_N27 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X94_Y15_N27; Fanout = 4; REG Node = 'state.Astop'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { state.Astop } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.511 ns) + CELL(0.438 ns) 0.949 ns switch1~0 2 COMB LCCOMB_X94_Y15_N20 2 " "Info: 2: + IC(0.511 ns) + CELL(0.438 ns) = 0.949 ns; Loc. = LCCOMB_X94_Y15_N20; Fanout = 2; COMB Node = 'switch1~0'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.949 ns" { state.Astop switch1~0 } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.718 ns) + CELL(2.602 ns) 4.269 ns switch2 3 PIN PIN_W23 0 " "Info: 3: + IC(0.718 ns) + CELL(2.602 ns) = 4.269 ns; Loc. = PIN_W23; Fanout = 0; PIN Node = 'switch2'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.320 ns" { switch1~0 switch2 } "NODE_NAME" } } { "train.v" "" { Text "E:/exercises/train_4/train.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.040 ns ( 71.21 % ) " "Info: Total cell delay = 3.040 ns ( 71.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.229 ns ( 28.79 % ) " "Info: Total interconnect delay = 1.229 ns ( 28.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "4.269 ns" { state.Astop switch1~0 switch2 } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "4.269 ns" { state.Astop {} switch1~0 {} switch2 {} } { 0.000ns 0.511ns 0.718ns } { 0.000ns 0.438ns 2.602ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.680 ns" { clock state.Astop } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "2.680 ns" { clock {} clock~combout {} state.Astop {} } { 0.000ns 0.000ns 1.291ns } { 0.000ns 0.852ns 0.537ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "4.269 ns" { state.Astop switch1~0 switch2 } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "4.269 ns" { state.Astop {} switch1~0 {} switch2 {} } { 0.000ns 0.511ns 0.718ns } { 0.000ns 0.438ns 2.602ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}