train.map.rpt

基于FPGA火车状态机的实现方法

+----------------------------------+-----------------+------------------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+------------------------------+
; train.v                          ; yes             ; User Verilog HDL File  ; E:/exercises/train_4/train.v ;
+----------------------------------+-----------------+------------------------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 9     ;
;                                             ;       ;
; Total combinational functions               ; 9     ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 8     ;
;     -- 3 input functions                    ; 0     ;
;     -- <=2 input functions                  ; 1     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 9     ;
;     -- arithmetic mode                      ; 0     ;
;                                             ;       ;
; Total registers                             ; 5     ;
;     -- Dedicated logic registers            ; 5     ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 15    ;
; Maximum fan-out node                        ; clock ;
; Maximum fan-out                             ; 5     ;
; Total fan-out                               ; 53    ;
; Average fan-out                             ; 1.83  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |train                     ; 9 (9)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 15   ; 0            ; |train              ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------+
; State Machine - |train|state                                                  ;
+-------------+-------------+-----------+-----------+-------------+-------------+
; Name        ; state.Astop ; state.Bin ; state.Ain ; state.ABout ; state.Bstop ;
+-------------+-------------+-----------+-----------+-------------+-------------+
; state.ABout ; 0           ; 0         ; 0         ; 0           ; 0           ;
; state.Ain   ; 0           ; 0         ; 1         ; 1           ; 0           ;
; state.Bin   ; 0           ; 1         ; 0         ; 1           ; 0           ;
; state.Astop ; 1           ; 0         ; 0         ; 1           ; 0           ;
; state.Bstop ; 0           ; 0         ; 0         ; 1           ; 1           ;
+-------------+-------------+-----------+-----------+-------------+-------------+


+------------------------------------------------------------+
; Registers Removed During Synthesis                         ;
+---------------------------------------+--------------------+
; Register name                         ; Reason for Removal ;
+---------------------------------------+--------------------+
; state~13                              ; Lost fanout        ;
; state~14                              ; Lost fanout        ;
; Total Number of Removed Registers = 2 ;                    ;
+---------------------------------------+--------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 5     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 5     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |train ;
+----------------+-------+----------------------------------------------+
; Parameter Name ; Value ; Type                                         ;
+----------------+-------+----------------------------------------------+
; ABout          ; 0     ; Signed Integer                               ;
; Ain            ; 1     ; Signed Integer                               ;
; Bin            ; 2     ; Signed Integer                               ;
; Astop          ; 3     ; Signed Integer                               ;
; Bstop          ; 4     ; Signed Integer                               ;
+----------------+-------+----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
    Info: Processing started: Tue Jul 10 13:11:03 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off train -c train
Info: Found 2 design units, including 1 entities, in source file debounce.vhd
    Info: Found design unit 1: debounce-TERASIC
    Info: Found entity 1: debounce
Info: Found 1 design units, including 1 entities, in source file train.v
    Info: Found entity 1: train
Info: Found 1 design units, including 1 entities, in source file Verilog2.v
    Info: Found entity 1: tb_train
Info: Elaborating entity "train" for the top level hierarchy
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "switch3" is stuck at GND
    Warning (13410): Pin "dirA[1]" is stuck at GND
    Warning (13410): Pin "dirB[1]" is stuck at GND
Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below.
    Info: Register "state~13" lost all its fanouts during netlist optimizations.
    Info: Register "state~14" lost all its fanouts during netlist optimizations.
Warning: Design contains 2 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "sensor5"
    Warning (15610): No output dependent on input pin "CLOCK_50"
Info: Implemented 24 device resources after synthesis - the final resource count might be different
    Info: Implemented 8 input pins
    Info: Implemented 7 output pins
    Info: Implemented 9 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
    Info: Peak virtual memory: 194 megabytes
    Info: Processing ended: Tue Jul 10 13:11:04 2012
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:02