train.map.summary

来自「基于FPGA火车状态机的实现方法」· SUMMARY 代码 · 共 15 行

Analysis & Synthesis Status : Successful - Tue Jul 10 13:11:04 2012
Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version
Revision Name : train
Top-level Entity Name : train
Family : Cyclone II
Total logic elements : 9
    Total combinational functions : 9
    Dedicated logic registers : 5
Total registers : 5
Total pins : 15
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0