📄 fzy2.mdl
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ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.196850, 0.196850, 0.196850, 0.196850]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Clock
Name "Clock"
Position [145, 195, 165, 215]
Decimation "10"
}
Block {
BlockType Constant
Name "Constant"
Position [20, 265, 50, 295]
Value "23"
}
Block {
BlockType Derivative
Name "Derivative"
Position [185, 345, 215, 375]
Port {
PortNumber 1
Name "ec"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Reference
Name "Fuzzy Logic \nController"
Ports [1, 1]
Position [460, 306, 520, 354]
FontName "Arial"
SourceBlock "fuzblock/Fuzzy Logic \nController"
SourceType "FIS"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
fis "fzy2"
}
Block {
BlockType Gain
Name "Gain 1"
Position [550, 315, 580, 345]
Gain "4"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Ke"
Position [245, 260, 275, 290]
Gain "3"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Kec"
Position [250, 345, 280, 375]
Gain "1.25"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Mux
Name "Mux"
Ports [2, 1]
Position [410, 311, 415, 349]
ShowName off
Inputs "2"
DisplayOption "bar"
}
Block {
BlockType Saturate
Name "Saturation"
Position [325, 270, 355, 300]
UpperLimit "2"
LowerLimit "-2"
}
Block {
BlockType Saturate
Name "Saturation1"
Position [330, 345, 360, 375]
}
Block {
BlockType Scope
Name "Scope"
Ports [1]
Position [760, 319, 790, 351]
Floating off
Location [188, 390, 512, 629]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
DataFormat "StructureWithTime"
SampleTime "0"
}
Block {
BlockType Sum
Name "Sum1"
Ports [2, 1]
Position [130, 270, 150, 290]
ShowName off
IconShape "round"
Inputs "|+-"
CollapseMode "All dimensions"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
Port {
PortNumber 1
Name "e"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType ToWorkspace
Name "To Workspace1"
Position [245, 195, 305, 225]
VariableName "t"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Structure With Time"
}
Block {
BlockType TransferFcn
Name "Transfer Fcn"
Position [600, 312, 660, 348]
Denominator "[3 1]"
}
Block {
BlockType TransferFcn
Name "Transfer Fcn1"
Position [500, 452, 560, 488]
Denominator "[1 1]"
}
Block {
BlockType TransportDelay
Name "Transport\nDelay"
Position [685, 315, 715, 345]
}
Line {
SrcBlock "Constant"
SrcPort 1
DstBlock "Sum1"
DstPort 1
}
Line {
Name "e"
Labels [0, 0]
SrcBlock "Sum1"
SrcPort 1
Points [15, 0]
Branch {
Labels [1, 0]
Points [60, 0]
DstBlock "Ke"
DstPort 1
}
Branch {
DstBlock "Derivative"
DstPort 1
}
}
Line {
SrcBlock "Ke"
SrcPort 1
Points [15, 0; 0, 10]
DstBlock "Saturation"
DstPort 1
}
Line {
Name "ec"
Labels [0, 0]
SrcBlock "Derivative"
SrcPort 1
DstBlock "Kec"
DstPort 1
}
Line {
SrcBlock "Kec"
SrcPort 1
DstBlock "Saturation1"
DstPort 1
}
Line {
SrcBlock "Clock"
SrcPort 1
Points [30, 0; 0, 5]
DstBlock "To Workspace1"
DstPort 1
}
Line {
SrcBlock "Saturation"
SrcPort 1
Points [15, 0; 0, 35]
DstBlock "Mux"
DstPort 1
}
Line {
SrcBlock "Saturation1"
SrcPort 1
Points [15, 0; 0, -20]
DstBlock "Mux"
DstPort 2
}
Line {
SrcBlock "Mux"
SrcPort 1
DstBlock "Fuzzy Logic \nController"
DstPort 1
}
Line {
SrcBlock "Fuzzy Logic \nController"
SrcPort 1
DstBlock "Gain 1"
DstPort 1
}
Line {
SrcBlock "Gain 1"
SrcPort 1
DstBlock "Transfer Fcn"
DstPort 1
}
Line {
SrcBlock "Transfer Fcn"
SrcPort 1
DstBlock "Transport\nDelay"
DstPort 1
}
Line {
SrcBlock "Transport\nDelay"
SrcPort 1
Points [10, 0; 0, 5; 5, 0]
Branch {
DstBlock "Scope"
DstPort 1
}
Branch {
Points [0, 80; -250, 0]
DstBlock "Transfer Fcn1"
DstPort 1
}
}
Line {
SrcBlock "Transfer Fcn1"
SrcPort 1
Points [0, 45; -460, 0; 0, -210]
DstBlock "Sum1"
DstPort 2
}
Annotation {
Name "Fuzzy Logic Library"
Position [227, 40]
FontName "Arial"
FontSize 12
FontWeight "bold"
}
}
}
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