xlli_bulverde_defs.inc

bootloader for mainstone2 system,main cpu is intel pxa chip.may need edit for your onw system

        .equ     xlli_ICMR_offset,(0x04)   @ Interrupt Controller Mask Register
        .equ     xlli_ICLR_offset,(0x08)   @ Interrupt Controller Level Register
        .equ     xlli_ICFP_offset,(0x0C)   @ Interrupt Controller FIQ pending Register
        .equ     xlli_ICPR_offset,(0x10)   @ Interrupt Controller Pending Register
        .equ     xlli_ICCR_offset,(0x14)   @ Interrupt Controller Control Register
        .equ     xlli_ICHP_offset,(0x18)   @ Interrupt Controller Highest Priority Reg
       .equ     xlli_ICMR2_offset,(0xA0)   @ Interrupt Controller Mask Register 2
       .equ     xlli_ICLR2_offset,(0xA4)   @ Interrupt Controller Level Register 2
       .equ     xlli_ICCR2_offset,(0xAC)   @ Interrupt Controller Control Register 2

@
@ CLOCK REGISTERS base address and register offsets from the base address
@ 

        .equ     xlli_CLKREGS_PHYSICAL_BASE,(0x41300000)

        .equ     xlli_CCCR_offset,(0x00)  @ Core Clock Configuration Register
        .equ     xlli_CKEN_offset,(0x04)  @ Clock-Enable Register
        .equ     xlli_OSCC_offset,(0x08)  @ Oscillator Configuration Register
        .equ     xlli_CCSR_offset,(0x0C)  @ Core Clock Status Register

    .equ     xlli_CCCR_A_Bit_Mask,(0x1 << 25)     @ "A" bit is bit 25 in CCCR
@
@ OS TIMER REGISTERS base address and register offsets from the base address
@ 

        .equ     xlli_OSTREGS_PHYSICAL_BASE,(0x40A00000)

       .equ     xlli_OSMR0_offset,(0x00)  @ OS Timer Match Register 0
       .equ     xlli_OSMR1_offset,(0x04)  @ OS Timer Match Register 1
       .equ     xlli_OSMR2_offset,(0x08)  @ OS Timer Match Register 2
       .equ     xlli_OSMR3_offset,(0x0C)  @ OS Timer Match Register 3

       .equ     xlli_OSCR0_offset,(0x10)  @ OS Timer Count Register 0
        .equ     xlli_OSSR_offset,(0x14)  @ OS Timer Status Register
        .equ     xlli_OWER_offset,(0x18)  @ OS Timer Watchdog Enable Register
        .equ     xlli_OIER_offset,(0x1C)  @ OS Timer Interrupt Enable Register

       .equ     xlli_OSCR4_offset,(0x40)  @ OS Timer Count Register 4
       .equ     xlli_OSCR5_offset,(0x44)  @ OS Timer Count Register 5
       .equ     xlli_OSCR6_offset,(0x48)  @ OS Timer Count Register 6
       .equ     xlli_OSCR7_offset,(0x4C)  @ OS Timer Count Register 7
       .equ     xlli_OSCR8_offset,(0x50)  @ OS Timer Count Register 8
       .equ     xlli_OSCR9_offset,(0x54)  @ OS Timer Count Register 9
      .equ     xlli_OSCR10_offset,(0x58)  @ OS Timer Count Register 10
      .equ     xlli_OSCR11_offset,(0x5C)  @ OS Timer Count Register 11

       .equ     xlli_OSMR4_offset,(0x80)  @ OS Timer Match Register 4
       .equ     xlli_OSMR5_offset,(0x84)  @ OS Timer Match Register 5
       .equ     xlli_OSMR6_offset,(0x88)  @ OS Timer Match Register 6
       .equ     xlli_OSMR7_offset,(0x8C)  @ OS Timer Match Register 7
       .equ     xlli_OSMR8_offset,(0x90)  @ OS Timer Match Register 8
       .equ     xlli_OSMR9_offset,(0x94)  @ OS Timer Match Register 9
      .equ     xlli_OSMR10_offset,(0x98)  @ OS Timer Match Register 10
      .equ     xlli_OSMR11_offset,(0x9C)  @ OS Timer Match Register 11

       .equ     xlli_OMCR4_offset,(0xC0)  @ OS Timer Match Control Register 4
       .equ     xlli_OMCR5_offset,(0xC4)  @ OS Timer Match Control Register 5
       .equ     xlli_OMCR6_offset,(0xC8)  @ OS Timer Match Control Register 6
       .equ     xlli_OMCR7_offset,(0xCC)  @ OS Timer Match Control Register 7
       .equ     xlli_OMCR8_offset,(0xD0)  @ OS Timer Match Control Register 8
       .equ     xlli_OMCR9_offset,(0xD4)  @ OS Timer Match Control Register 9
      .equ     xlli_OMCR10_offset,(0xD8)  @ OS Timer Match Control Register 10
      .equ     xlli_OMCR11_offset,(0xDC)  @ OS Timer Match Control Register 11

           .equ     xlli_OSSR_ALL,(0xFFF) @ Match register status "sticky bits"
            .equ     xlli_OIER_E1,(0x002) @ Interrupt enable bit for match register #1

@
@ REAL TIME CLOCK (RTC) REGISTERS base address and register offsets from the base address
@ 

      .equ     xlli_RTCREGS_PHYSICAL_BASE,(0x04090000)

        .equ     xlli_RCNR_offset,(0x00)  @ RTC Counter Register
        .equ     xlli_RTAR_offset,(0x04)  @ RTC Alarm Register
        .equ     xlli_RTSR_offset,(0x08)  @ RTC Status Register
        .equ     xlli_RTTR_offset,(0x0C)  @ RTC Timer Trim Register
        .equ     xlli_RDCR_offset,(0x10)  @ RTC Day Counter Register
        .equ     xlli_RYCR_offset,(0x14)  @ RTC Year Counter Register 
       .equ     xlli_RDAR1_offset,(0x18)  @ RTC Day Alarm Register 1
       .equ     xlli_RYAR1_offset,(0x1C)  @ RTC Year Alarm Register 2
       .equ     xlli_RDAR2_offset,(0x20)  @ RTC Day Alarm Register 2
       .equ     xlli_RYAR2_offset,(0x24)  @ RTC Year Alarm Register 2
        .equ     xlli_SWCR_offset,(0x28)  @ Stopwatch Counter Register
       .equ     xlli_SWAR1_offset,(0x2C)  @ Stopwatch Alarm Register 1
       .equ     xlli_SWAR2_offset,(0x30)  @ Stopwatch Alarm Register 2
        .equ     xlli_PICR_offset,(0x34)  @ Periodic Interrupt Counter Register
        .equ     xlli_PIAR_offset,(0x38)  @ Periodic Interrupt Alarm Register


@ Interrupt Controller bit defs

           .equ     xlli_OSCC_OOK,(0x01)  @ Oscillator OK bit
           .equ     xlli_OSCC_OON,(0x02)  @ Timekeeping (32.768KHz) Osc bit
       .equ     xlli_OSCC_TOUT_EN,(0x04)  @ Timekeeping Output enable
        .equ     xlli_OSCC_PIO_EN,(0x08)  @ Processor Oscillator Output Enable

@
@ Coprocessor 15 data bits
@ 

  .equ     xlli_control_icache,(0x1000)  @ bit 12 -  i-cache bit
     .equ     xlli_control_btb,(0x0800)  @ bit 11 -  btb bit
       .equ     xlli_control_r,(0x0200)  @ Bit 9
       .equ     xlli_control_s,(0x0100)  @ Bit 8
  .equ     xlli_control_dcache,(0x0004)  @ Bit 2  -  d-cache bit
     .equ     xlli_control_mmu,(0x0001)  @ Bit 0  -  MMU bit


@
@ CP 15 related settings
@

                   .equ     xlli_PID,(0x00)
                  .equ     xlli_DACR,(0x01)
        .equ     xlli_CONTROL_DCACHE,(0x04)
   .equ     xlli_CONTROL_MINIDATA_01,(0x10)
           .equ     xlli_CONTROL_BTB,(0x800)   @ Brach Target Buffer bit

@
@ register bit masks - RCSR
@
         .equ     xlli_RCSR_HWR,(0x01)
         .equ     xlli_RCSR_WDR,(0x02)
         .equ     xlli_RCSR_SMR,(0x04)
         .equ     xlli_RCSR_GPR,(0x08)
         .equ     xlli_RCSR_ALL,(0xF)


@
@  CPSR Processor constants

   .equ       xlli_CPSR_Mode_MASK,(0x0000001F)
    .equ       xlli_CPSR_Mode_USR,(0x10)
    .equ       xlli_CPSR_Mode_FIQ,(0x11)
    .equ       xlli_CPSR_Mode_IRQ,(0x12)
    .equ       xlli_CPSR_Mode_SVC,(0x13)
    .equ       xlli_CPSR_Mode_ABT,(0x17)
    .equ       xlli_CPSR_Mode_UND,(0x1B)
    .equ       xlli_CPSR_Mode_SYS,(0x1F)

       .equ       xlli_CPSR_I_Bit,(0x80)
       .equ       xlli_CPSR_F_Bit,(0x40)


    .equ       xlli_PWRMODE_SLEEP,(0x00000003) @ Value for cp14: Reg7 to induce sleep.
@     Bit settings
@
      .equ     xlli_BIT_0,0x00000001
      .equ     xlli_BIT_1,0x00000002
      .equ     xlli_BIT_2,0x00000004
      .equ     xlli_BIT_3,0x00000008
      .equ     xlli_BIT_4,0x00000010
      .equ     xlli_BIT_5,0x00000020
      .equ     xlli_BIT_6,0x00000040
      .equ     xlli_BIT_7,0x00000080
      .equ     xlli_BIT_8,0x00000100
      .equ     xlli_BIT_9,0x00000200
     .equ     xlli_BIT_10,0x00000400
     .equ     xlli_BIT_11,0x00000800
     .equ     xlli_BIT_12,0x00001000
     .equ     xlli_BIT_13,0x00002000
     .equ     xlli_BIT_14,0x00004000
     .equ     xlli_BIT_15,0x00008000
     .equ     xlli_BIT_16,0x00010000
     .equ     xlli_BIT_17,0x00020000
     .equ     xlli_BIT_18,0x00040000
     .equ     xlli_BIT_19,0x00080000
     .equ     xlli_BIT_20,0x00100000
     .equ     xlli_BIT_21,0x00200000
     .equ     xlli_BIT_22,0x00400000
     .equ     xlli_BIT_23,0x00800000
     .equ     xlli_BIT_24,0x01000000
     .equ     xlli_BIT_25,0x02000000
     .equ     xlli_BIT_26,0x04000000
     .equ     xlli_BIT_27,0x08000000
     .equ     xlli_BIT_28,0x10000000
     .equ     xlli_BIT_29,0x20000000
     .equ     xlli_BIT_30,0x40000000
     .equ     xlli_BIT_31,0x80000000