xlli_bulverde_defs.inc

bootloader for mainstone2 system,main cpu is intel pxa chip.may need edit for your onw system

@*********************************************************************************
@
@ Copyright (C) 2004, Intel Corporation
@
@ This software program is licensed subject to the GNU General Public License
@ (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html
@
@*********************************************************************************
@
@  FILENAME:       xlli_Bulverde_defs.inc (Core processor address definitions for PXA27x)
@
@ LAST MODIFIED:   5-Apr-2004
@
@******************************************************************************
@
@ Include file for PXA27x Processor based
@ Cross Platform Low Level Initialization  (XLLI)
@

@
@ GENERAL PURPOSE I/O (GPIO) base address and register offsets from the base address
@

	 .equ 	xlli_GPIOREGS_PHYSICAL_BASE,0x40E00000

@ GPIO register offsets from the base address

    .equ    xlli_GPLR0_offset,(0x000)  @ GPIO Level registers
    .equ    xlli_GPLR1_offset,(0x004)
    .equ    xlli_GPLR2_offset,(0x008)
    .equ    xlli_GPLR3_offset,(0x100)

    .equ    xlli_GPDR0_offset,(0x00C)  @ GPIO Direction registers
    .equ    xlli_GPDR1_offset,(0x010)
    .equ    xlli_GPDR2_offset,(0x014)
    .equ    xlli_GPDR3_offset,(0x10C)

    .equ    xlli_GPSR0_offset,(0x018)  @ GPIO Set registers
    .equ    xlli_GPSR1_offset,(0x01C)
    .equ    xlli_GPSR2_offset,(0x020)
    .equ    xlli_GPSR3_offset,(0x118)

    .equ    xlli_GPCR0_offset,(0x024)  @ GPIO Clear registers
    .equ    xlli_GPCR1_offset,(0x028)
    .equ    xlli_GPCR2_offset,(0x02C)
    .equ    xlli_GPCR3_offset,(0x124)

  .equ    xlli_GAFR0_L_offset,(0x054)  @ GPIO Alternate function registers (Bits 15:0)
  .equ    xlli_GAFR0_U_offset,(0x058)  @ Bits 31:16
  .equ    xlli_GAFR1_L_offset,(0x05c)  @ Bits 47:32
  .equ    xlli_GAFR1_U_offset,(0x060)  @ Bits 63:48
  .equ    xlli_GAFR2_L_offset,(0x064)  @ Bits 79:64
  .equ    xlli_GAFR2_U_offset,(0x068)  @ Bits 95:80
  .equ    xlli_GAFR3_L_offset,(0x06C)  @ Bits 111:96
  .equ    xlli_GAFR3_U_offset,(0x070)  @ Bits 127:112

@
@ POWER MANAGER base address and register offsets from the base address
@

	 .equ 	xlli_PMRCREGS_PHYSICAL_BASE,0x40F00000 

        .equ     xlli_PMCR_offset,(0x00)  @ Power Manager Control Register
        .equ     xlli_PSSR_offset,(0x04)  @ Power Manager Sleep Status Register
        .equ     xlli_PSPR_offset,(0x08)  @ Power Manager Scratch Pad Register
        .equ     xlli_PWER_offset,(0x0C)  @ Power Manager Wake-up Enable Register
        .equ     xlli_PRER_offset,(0x10)  @ Power Manager GPIO Rising-edge Detect Enable Register
        .equ     xlli_PFER_offset,(0x14)  @ Power Manager GPIO Falling-edge Detect Enable Register
        .equ     xlli_PEDR_offset,(0x18)  @ Power Manager GPIO Edge Detect Status Register
        .equ     xlli_PCFR_offset,(0x1C)  @ Power Manager General Configuration Register
       .equ     xlli_PGSR0_offset,(0x20)  @ Power Manager GPIO Sleep State Register for GP [31-0]
       .equ     xlli_PGSR1_offset,(0x24)  @ Power Manager GPIO Sleep State Register for GP [63-32]
       .equ     xlli_PGSR2_offset,(0x28)  @ Power Manager GPIO Sleep State Register for GP [95-64]
       .equ     xlli_PGSR3_offset,(0x2C)  @ Power Manager GPIO Sleep State Register for GP [120-96]
        .equ     xlli_RCSR_offset,(0x30)  @ Reset Controller Status Register
        .equ     xlli_PSLR_offset,(0x34)  @ Power Manager Sleep Mode Config Register
        .equ     xlli_PSTR_offset,(0x38)  @ Power Manager Standby Mode Config Register
        .equ     xlli_PSNR_offset,(0x3C)  @ Power Manager Sense Moce Config Register
        .equ     xlli_PVCR_offset,(0x40)  @ Power Manager Voltage Change Control Register
        .equ     xlli_PKWR_offset,(0x50)  @ Power Manager Keyboard Wake-up Enable Register
        .equ     xlli_PKSR_offset,(0x54)  @ Power Manager Keyboard Edge-Detect Status Register
      .equ     xlli_PI2DBR_offset,(0x188) @ Power I2C Data Buffer Register
       .equ     xlli_PI2CR_offset,(0x190) @ Power I2C Control Register
       .equ     xlli_PI2SR_offset,(0x198) @ Power I2C Status Register
      .equ     xlli_PI2SAR_offset,(0x1A0) @ Power I2C Slave Address Register

@
@ POWER MANAGER register bit masks 
@
           .equ     xlli_PSSR_SSS,(0x01)  @ Software Sleep Status
           .equ     xlli_PSSR_BFS,(0x02)  @ Battery Fault Status
           .equ     xlli_PSSR_VFS,(0x04)  @ VCC Fault Status
            .equ     xlli_PSSR_PH,(0x10)  @ Peripheral Control Hold
           .equ     xlli_PSSR_RDH,(0x20)  @ Read Disable Hold

          .equ     xlli_PCFR_OPDE,(0x01)  @ Processor (13MHz) osc power-down enable
            .equ     xlli_PCFR_FP,(0x02)  @ Float PCMCIA during sleep modes
            .equ     xlli_PCFR_FS,(0x04)  @ Float Static Chip Selects
        .equ     xlli_PCFR_GPR_EN,(0x10)  @ GPIO 1 performs GPIO reset
      .equ     xlli_PCFR_SYSEN_EN,(0x20)  @ SYS_EN pin
       .equ     xlli_PCFR_PI2C_EN,(0x40)  @
         .equ     xlli_PCFR_DC_EN,(0x80)  @ Deep-Sleep Mode
           .equ     xlli_PCFR_FVC,(0x400) @
         .equ     xlli_PCFR_L1_EN,(0x800) @
         .equ     xlli_PCFR_GPROD,(0x1000) @
            .equ     xlli_PCFR_PO,(0x4000) @
            .equ     xlli_PCFR_RO,(0x8000) @
      .equ     xlli_PCFR_USEDBITS,(xlli_PCFR_OPDE | xlli_PCFR_FP | xlli_PCFR_FS | xlli_PCFR_GPR_EN | xlli_PCFR_SYSEN_EN| xlli_PCFR_PI2C_EN | xlli_PCFR_DC_EN | xlli_PCFR_FVC | xlli_PCFR_L1_EN| xlli_PCFR_GPROD | xlli_PCFR_PO | xlli_PCFR_RO)
           .equ     xlli_PWER_WE0,(0x01)          @ Wake-up Enable GPIO pin 0
           .equ     xlli_PWER_WE1,(0x02)          @ Wake-up Enable GPIO pin 1
         .equ     xlli_PWER_WERTC,(0x80000000)    @ RTC Standby, Wake-up Enable-

@
@ MEMORY CONTROLLER base address and register offsets from the base address 
@

 .equ     xlli_MEMORY_CONFIG_BASE,0x48000000

      .equ     xlli_MDCNFG_offset,(0x00)
      .equ     xlli_MDREFR_offset,(0x04)
        .equ     xlli_MSC0_offset,(0x08)
        .equ     xlli_MSC1_offset,(0x0C)
        .equ     xlli_MSC2_offset,(0x10)
        .equ     xlli_MECR_offset,(0x14)
       .equ     xlli_SXLCR_offset,(0x18)
      .equ     xlli_SXCNFG_offset,(0x1C)
     .equ     xlli_FLYCNFG_offset,(0x20)
       .equ     xlli_SXMRS_offset,(0x24)                                       
      .equ     xlli_MCMEM0_offset,(0x28)
      .equ     xlli_MCMEM1_offset,(0x2C)
      .equ     xlli_MCATT0_offset,(0x30)
      .equ     xlli_MCATT1_offset,(0x34)
       .equ     xlli_MCIO0_offset,(0x38)
       .equ     xlli_MCIO1_offset,(0x3C)
       .equ     xlli_MDMRS_offset,(0x40)
    .equ     xlli_BOOT_DEF_offset,(0x44)
    .equ     xlli_ARB_CNTL_offset,(0x48)
     .equ     xlli_BSCNTR0_offset,(0x4C)
     .equ     xlli_BSCNTR1_offset,(0x50)
   .equ     xlli_LCDBSCNTR_offset,(0x54)
     .equ     xlli_MDMRSLP_offset,(0x58)
     .equ     xlli_BSCNTR2_offset,(0x5C)
     .equ     xlli_BSCNTR3_offset,(0x60)

@ Memory Controller bit defs

       .equ     xlli_MDREFR_K0DB4,(0x20000000)    @ Sync Static Clock 0 divide by 4 control/status
      .equ     xlli_MDREFR_K2FREE,(0x02000000)    @ Set to force SDCLK[2] to be free running
      .equ     xlli_MDREFR_K1FREE,(0x01000000)    @ Set to force SDCLK[1] to be free running
      .equ     xlli_MDREFR_K0FREE,(0x00800000)    @ Set to force SDCLK[0] to be free running
      .equ     xlli_MDREFR_SLFRSH,(0x00400000)    @ Self Refresh Control Status bit
         .equ     xlli_MDREFR_APD,(0x00100000)    @ Auto Power Down bit
       .equ     xlli_MDREFR_K2DB2,(0x00080000)    @ SDRAM clock pin 2 divide by 2 control/status
       .equ     xlli_MDREFR_K1DB2,(0x00020000)    @ SDRAM clock pin 1 divide by 2 control/status
       .equ     xlli_MDREFR_K1RUN,(0x00010000)    @ SDRAM clock pin 1 run/control status
       .equ     xlli_MDREFR_E1PIN,(0x00008000)    @ SDRAM clock Enable pin 1 level control/status
       .equ     xlli_MDREFR_K0DB2,(0x00004000)    @ Sync Static Memory Clock divide by 2 control/status
       .equ     xlli_MDREFR_K0RUN,(0x00002000)    @ Sync Static Memory Clock Pin 0
       .equ     xlli_MDREFR_E0PIN,(0x00000100)    @ SDRAM clock enable pin 0 (Cotulla ONLY!!)

         .equ     xlli_MDCNFG_DE0,(0x00000001)    @ SDRAM enable bit for partition 0
         .equ     xlli_MDCNFG_DE1,(0x00000002)    @ SDRAM enable bit for partition 1
         .equ     xlli_MDCNFG_DE2,(0x00010000)    @ SDRAM enable bit for partition 2
         .equ     xlli_MDCNFG_DE3,(0x00020000)    @ SDRAM enable bit for partition 3
       .equ     xlli_MDCNFG_DWID0,(0x00000004)    @ SDRAM bus width (clear = 32 bits, set = 16 bits)

@
@ INTERNAL MEMORY CONTROLLER base address and register offsets from the base address 
@

        .equ     xlli_IMEMORY_CONFIG_BASE,(0x58000000)

              .equ     xlli_IMPMCR_offset,(0x00)  @ Internal Memory Power Manager Control Register
              .equ     xlli_IMPMSR_offset,(0x08)  @ Internal Memory Power Management Status Register


@
@ INTERRUPT CONTROLLER base address and register offsets from the base address
@ 

      .equ     xlli_INTERREGS_PHYSICAL_BASE,(0x40D00000)

        .equ     xlli_ICIP_offset,(0x00)   @ Interrupt Controller IRQ Pending Register