📄 xlli_mainstone_defs.inc
字号:
.equ xlli_DTC_143,(0x02000200) @ 143 MHz setting - SDCLK Halved .equ xlli_DTC_149,(0x02000200) @ 149 MHz setting - SDCLK Halved .equ xlli_DTC_156,(0x02000200) @ 156 MHz setting - SDCLK Halved .equ xlli_DTC_162,(0x02000200) @ 162 MHz setting - SDCLK Halved .equ xlli_DTC_169,(0x02000200) @ 169 MHz setting - SDCLK Halved .equ xlli_DTC_175,(0x02000200) @ 175 MHz setting - SDCLK Halved .equ xlli_DTC_182,(0x02000200) @ 182 MHz setting - SDCLK Halved .equ xlli_DTC_188,(0x02000200) @ 188 MHz setting - SDCLK Halved .equ xlli_DTC_195,(0x02000200) @ 195 MHz setting - SDCLK Halved .equ xlli_DTC_201,(0x03000300) @ 201 MHz setting - SDCLK Halved .equ xlli_DTC_208,(0x03000300) @ 208 MHz setting - SDCLK Halved@@ Optimal values for DRI settings for various MemClk settings (MDREFR)@ .equ xlli_DRI_13,(0x002) @ 13 MHz setting .equ xlli_DRI_19,(0x003) .equ xlli_DRI_26,(0x004) @ 26 MHz setting .equ xlli_DRI_32,(0x006) .equ xlli_DRI_39,(0x007) @ 39 MHz setting .equ xlli_DRI_45,(0x009) .equ xlli_DRI_52,(0x00A) @ 52 MHz setting .equ xlli_DRI_58,(0x00C) .equ xlli_DRI_65,(0x00D) @ 65 MHz setting .equ xlli_DRI_68,(0x00E) .equ xlli_DRI_71,(0x00F) @ 71 MHz setting .equ xlli_DRI_74,(0x010) .equ xlli_DRI_78,(0x010) @ 78 MHz setting .equ xlli_DRI_81,(0x011) .equ xlli_DRI_84,(0x012) @ 84 MHz setting .equ xlli_DRI_87,(0x013) .equ xlli_DRI_91,(0x013) @ 91 MHz setting .equ xlli_DRI_94,(0x014) @ 94 MHz setting .equ xlli_DRI_97,(0x015) @ 97 MHz setting .equ xlli_DRI_100,(0x016) @ 100 MHz setting .equ xlli_DRI_104,(0x016) @ 104 MHz setting .equ xlli_DRI_110,(0x018) .equ xlli_DRI_117,(0x019) @ 117 MHz setting .equ xlli_DRI_124,(0x01B) .equ xlli_DRI_130,(0x01C) @ 130 MHz setting .equ xlli_DRI_136,(0x01E) .equ xlli_DRI_143,(0x01F) .equ xlli_DRI_149,(0x021) .equ xlli_DRI_156,(0x022) .equ xlli_DRI_162,(0x024) .equ xlli_DRI_169,(0x025) @ 169 MHz setting .equ xlli_DRI_175,(0x027) .equ xlli_DRI_182,(0x028) .equ xlli_DRI_188,(0x02A) .equ xlli_DRI_195,(0x02B) .equ xlli_DRI_201,(0x02D) .equ xlli_DRI_208,(0x02E) @ 208 MHz setting .else @ ELSE not 16 bit SDRAM width .equ xlli_DTC_13,(0x00000000) @ 13 MHz setting .equ xlli_DTC_19,(0x00000000) @ 19 MHz setting .equ xlli_DTC_26,(0x00000000) @ 26 MHz setting .equ xlli_DTC_32,(0x00000000) @ 32 MHz setting .equ xlli_DTC_39,(0x00000000) @ 39 MHz setting .equ xlli_DTC_45,(0x00000000) @ 45 MHz setting .equ xlli_DTC_52,(0x00000000) @ 52 MHz setting .equ xlli_DTC_58,(0x01000100) @ 58 MHz setting .equ xlli_DTC_65,(0x01000100) @ 65 MHz setting .equ xlli_DTC_68,(0x01000100) @ 68 MHz setting .equ xlli_DTC_71,(0x01000100) @ 71 MHz setting .equ xlli_DTC_74,(0x01000100) @ 74 MHz setting .equ xlli_DTC_78,(0x01000100) @ 78 MHz setting .equ xlli_DTC_81,(0x01000100) @ 81 MHz setting .equ xlli_DTC_84,(0x01000100) @ 84 MHz setting .equ xlli_DTC_87,(0x01000100) @ 87 MHz setting .equ xlli_DTC_91,(0x02000200) @ 91 MHz setting .equ xlli_DTC_94,(0x02000200) @ 94 MHz setting .equ xlli_DTC_97,(0x02000200) @ 97 MHz setting .equ xlli_DTC_100,(0x02000200) @ 100 MHz setting .equ xlli_DTC_104,(0x02000200) @ 104 MHz setting .equ xlli_DTC_110,(0x01000100) @ 110 MHz setting - SDCLK Halved .equ xlli_DTC_117,(0x01000100) @ 117 MHz setting - SDCLK Halved .equ xlli_DTC_124,(0x01000100) @ 124 MHz setting - SDCLK Halved .equ xlli_DTC_130,(0x01000100) @ 130 MHz setting - SDCLK Halved .equ xlli_DTC_136,(0x01000100) @ 136 MHz setting - SDCLK Halved .equ xlli_DTC_143,(0x01000100) @ 143 MHz setting - SDCLK Halved .equ xlli_DTC_149,(0x01000100) @ 149 MHz setting - SDCLK Halved .equ xlli_DTC_156,(0x01000100) @ 156 MHz setting - SDCLK Halved .equ xlli_DTC_162,(0x01000100) @ 162 MHz setting - SDCLK Halved .equ xlli_DTC_169,(0x01000100) @ 169 MHz setting - SDCLK Halved .equ xlli_DTC_175,(0x01000100) @ 175 MHz setting - SDCLK Halved .equ xlli_DTC_182,(0x02000200) @ 182 MHz setting - SDCLK Halved - Close to edge, so bump up .equ xlli_DTC_188,(0x02000200) @ 188 MHz setting - SDCLK Halved - Close to edge, so bump up .equ xlli_DTC_195,(0x02000200) @ 195 MHz setting - SDCLK Halved - Close to edge, so bump up .equ xlli_DTC_201,(0x02000200) @ 201 MHz setting - SDCLK Halved - Close to edge, so bump up .equ xlli_DTC_208,(0x02000200) @ 208 MHz setting - SDCLK Halved - Close to edge, so bump up@@ Optimal values for DRI settings for various MemClk settings (MDREFR)@ .equ xlli_DRI_13,(0x002) @ 13 MHz setting .equ xlli_DRI_19,(0x003) .equ xlli_DRI_26,(0x005) @ 26 MHz setting .equ xlli_DRI_32,(0x006) .equ xlli_DRI_39,(0x008) @ 39 MHz setting .equ xlli_DRI_45,(0x00A) .equ xlli_DRI_52,(0x00B) @ 52 MHz setting .equ xlli_DRI_58,(0x00D) .equ xlli_DRI_65,(0x00E) @ 65 MHz setting .equ xlli_DRI_68,(0x00F) .equ xlli_DRI_71,(0x010) @ 71 MHz setting .equ xlli_DRI_74,(0x011) .equ xlli_DRI_78,(0x012) @ 78 MHz setting .equ xlli_DRI_81,(0x012) .equ xlli_DRI_84,(0x013) @ 84 MHz setting .equ xlli_DRI_87,(0x014) .equ xlli_DRI_91,(0x015) @ 91 MHz setting .equ xlli_DRI_94,(0x016) @ 94 MHz setting .equ xlli_DRI_97,(0x016) @ 97 MHz setting .equ xlli_DRI_100,(0x017) @ 100 MHz setting .equ xlli_DRI_104,(0x018) @ 104 MHz setting .equ xlli_DRI_110,(0x01A) .equ xlli_DRI_117,(0x01B) @ 117 MHz setting .equ xlli_DRI_124,(0x01D) .equ xlli_DRI_130,(0x01E) @ 130 MHz setting .equ xlli_DRI_136,(0x020) .equ xlli_DRI_143,(0x021) .equ xlli_DRI_149,(0x023) .equ xlli_DRI_156,(0x025) .equ xlli_DRI_162,(0x026) .equ xlli_DRI_169,(0x028) @ 169 MHz setting .equ xlli_DRI_175,(0x029) .equ xlli_DRI_182,(0x02B) .equ xlli_DRI_188,(0x02D) .equ xlli_DRI_195,(0x02E) .equ xlli_DRI_201,(0x030) .equ xlli_DRI_208,(0x031) @ 208 MHz setting .endif @ xlli_SDRAM_WIDTH_16_BIT@@ SDRAM Settings@ .ifdef xlli_SDRAM_WIDTH_16_BIT .equ xlli_MDCNFG_value,(0x00002BCC) @ SDRAM Config Reg (MCP Version) .else .equ xlli_MDCNFG_value,(0x00000AC8) @ SDRAM Config Reg (Non-MCP Version) .endif .equ xlli_MDMRS_value,(0x00000000) @ SDRAM Mode Reg Set Config Reg@@ MEMORY PHYSICAL BASE ADDRESS(S)@ .equ xlli_SRAM_PHYSICAL_BASE,(0X5C000000) @ Physical base address for SRAM .equ xlli_SDRAM_PHYSICAL_BASE,(0xA0000000) @ Physical base address for SDRAM@@ CORE, SYSTEM BUS, MEMORY BUS Default frequency setting for Mainstone@ .equ xlli_CCCR_value,(0x00000107) @ PXA27x (HW reset value to start)@@ Clock Enable Register (CKEN) setting@ .equ xlli_CKEN_value,(0x00400240) @ Data to be set into the clock enable register @ Bit 6 enables FFUART @ bit 9 enables OS timers @ Bit 22 enables memory clock@@ Address where system configuration data is stored@ .equ xlli_SCR_data,0x5C03FFFC @ Address of system config data@@ Misc constants@ .equ xlli_MemSize_1Mb,0x00100000 .ifdef xlli_SDRAM_SIZE_32_MB .equ xlli_p_PageTable,0xA1FFC000 @ Base address for memory Page Table (MCP version) .else .equ xlli_p_PageTable,0xA3FFC000 @ Base address for memory Page Table (Non-MCP version) .endif .equ xlli_s_PageTable,0x00004000 @ Page Table size (4K words - 16 Kb) .equ xlli_FLASH_WRITE_CMD,0x0060 @ Code for writing to flash .equ xlli_FLASH_WCONF_CMD,0x0003 @ Code to confirm write to flash .equ xlli_FLASH_READ_CMD,0x00FF @ Code to place flash in read mode .equ xlli_FLASH_READQUERY_CMD,0x0098 @ Code to place flash in a 'query CFI' mode@@ Note 1: For the current L3/L18 flash, it has a maximium frequency of 52MHz. In addition, the SXCNFG.LC value is based on the@ SDClk presented to the flash, not the MEMClk as with most other Memory Controller settings, a bit odd, but so be it.@@ Note 2: We have just optimized these values for 52MHz SDClk to the Flash part. The OEM could optimize this for other SDClk values,@ but as there are so many, and the predominant Intel supported frequencies put the flash part into 52MHz operation, it@ made more sense to focus on the code, as each OEM will decide how best to run/optimize their platform.@@ Explaination of RCR value:@@ Read Mode = 0x0 = Sync. Mode@ Latency Count = 0x5@ Wait Polarity = 0x0 = Wait active low@ Data Hold = 0x0 = Hold for 1 clock@ Wait Delay = 0x1 = Wait de-asserted 1 dcycle before valid data@ Burst Sequence = 0x1 = Linear@ Clock Edge = 0x1 = Rising@ Burst Wrap = 0x0 = wrap@ Burst length = 0x3 = 16 word burst@@ Note on Burst Length: Spacial locality suggests that having a burst of 16 will give better results than that of 8, however,@ be aware that 8 words is a cache line, so it may be more beneficial to revert to a burst length of 8 words per@ burst as opposed to 16 words per burst@ .equ xlli_FLASH_RCR16_value,0x25C3<<1 @ Value to set flash into sync mode - optimal RC.LC value for 52MHz flash is 5 .equ xlli_FLASH_RCR32_value,0x25C3<<2 @ Value to set flash into sync mode - optimal RC.LC value for 52MHz flash is 5@@ Value below is simply to align with the settings put in for the flash RCR value@ .equ xlli_SXCNFG_sync_value,0x7011 @ SXCNFG value for sync flash operation - optimal SXCNFG.LC value for 52MHz flash is 4@@ Values to put the flash back into Asynchronous mode@ .equ xlli_FLASH_ASYNC_RCR16_value,0xA5C2<<1 @ Value to set flash into sync mode - optimal RC.LC value for 52MHz flash is 5 .equ xlli_FLASH_ASYNC_RCR32_value,0xA5C2<<2 @ Value to set flash into sync mode - optimal RC.LC value for 52MHz flash is 5 .equ xlli_SXCNFG_async_value,0x7010 @ SXCNFG value for sync flash operation - optimal SXCNFG.LC value for 52MHz flash is 4@@ Types of flash that XLLI can discover include:@@ TYPE CODE RANGE@ ---- ----------------@ J3 = 0x16 -> 0x18@ K3 = 0x8801 -> 0x8803@ K18 = 0x8805 -> 0x8807@ L18 = 0x880E -> 0x8810@ L3 = 0x8812 -> 0x8815@ .equ xlli_J3_FlashID_Code,0x0018 @ return value of J3 in parallel mode .equ xlli_K3_FlashID_Code,0x8803 @ use the upper (so can compare as <= .equ xlli_K18_FlashID_Code,0x8807 @ use the upper (so can compare as <= .equ xlli_L18_FlashID_Code,0x8810 @ use the upper (so can compare as <= .equ xlli_L3_FlashID_Code,0x8815 @ use the upper (so can compare as <=@@ Special conditional required for Power On SelfTest (POST) build@ .ifdef POST_BUILD .equ xlli_v_xbBOOTROM,0x04000000 @ Required for POST .else .equ xlli_v_xbBOOTROM,0x00000000 @ Everything else .endif ⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -