startup.s

smdk2416 wince source code/BSP

	INCLUDE kxarm.h
	INCLUDE armmacros.s
	INCLUDE s3c2450.inc

MemoryMap	EQU    0x2a4
BANK_SIZE	EQU    0x00100000      ; 1MB per bank in MemoryMap array
BANK_SHIFT	EQU    20

;------------------------------------------------------------------------------
;   Define RAM space for the Page Tables:

PHYBASE		EQU    0x30000000		; physical start
PTs			EQU    0x30010000		; 1st level page table address (PHYBASE + 0x10000)

;------------------------------------------------------------------------------
; Data Cache Characteristics.
;


	[ BSP_TYPE = BSP_SMDK2443
DCACHE_LINES_PER_SET_BITS       EQU     6
DCACHE_LINES_PER_SET            EQU     64
DCACHE_NUM_SETS                 EQU     8
DCACHE_SET_INDEX_BIT            EQU     (32 - DCACHE_LINES_PER_SET_BITS)
DCACHE_LINE_SIZE                EQU     32
	]

;926EJ, 2450

	[ BSP_TYPE = BSP_SMDK2450
DCACHE_LINES_PER_SET_BITS       EQU     2
DCACHE_LINES_PER_SET            EQU     4
DCACHE_NUM_SETS                 EQU     128
DCACHE_SET_INDEX_BIT            EQU     (32 - DCACHE_LINES_PER_SET_BITS)
DCACHE_LINE_SIZE                EQU     32
	]	
	TEXTAREA
							; save room for interrupt vectors.

	IMPORT  main

; Set up the MMU and Dcache for bootloader.
;
; This routine will initialize the first-level page table based up the contents
; of the MemoryMap array and enable the MMU and caches.
;
; Copy the image to RAM if it's not already running there.
;
; Include Files

; Defines


;------------------------------------------------------------------------------
; System clock configuration

;PLLVAL      EQU     (((110 << 12) + (3 << 4) + 1))	; 399Mhz
;CLKDIVVAL	EQU 7	; 0x0 = 1:1:1, 0x1 = 1:1:2, 0x2 = 1:2:2, 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
;UPLLVAL		EQU (((60 << 12) + (0x4 << 4) + 0x2))	; 48MHz

PLLVAL		EQU (((116 << 12) + (5 << 4) + 1))
CLKDIVVAL	EQU 15	; 0x8 = 1:1:1, 0x9 = 1:1:2, 0xa = 1:2:2, 0xb = 1:2:4, 0xc = 1:4:4, 0xd = 1:4:8, 0xe = 1:3:3, 0xf = 1:3:6
UPLLVAL		EQU (((60 << 12) + (0x4 << 4) + 0x1))	; 96MHz


;---------------------------------------------------------------------------
;	4 LED light function
;	The LEDs are located below AMD Flash ROM

	[BSP_TYPE = BSP_SMDK2443 
	MACRO
	LED_ON	$data

	LDR		r10, =0x56000054
	LDR		r11, =$data
	MOV		r11, r11, lsl #4	; [7:4]
  	STR		r11, [r10]

  	MEND
  	]
;---------------------------------------------------------------------------

; External Variables

; External Functions

; Global Variables

; Local Variables

; Local Functions

;-------------------------------------------------------------------------------
;   Function: Startup
;
;   Main entry point for CPU initialization.
;

	STARTUPTEXT

	LEAF_ENTRY	StartUp

	; Jump over power-off code.
	b		ResetHandler

ResetHandler

	;---------------------------
	; Make sure that TLB & cache are consistent

	mov		r0, #0
	mcr		p15, 0, r0, c8, c7, 0		; flush both TLB
	mcr		p15, 0, r0, c7, c5, 0		; invalidate instruction cache
	mcr		p15, 0, r0, c7, c6, 0		; invalidate data cache

		[ {FALSE}

	;------------------------
	; disable the watchdog timer.

	ldr		r0, =WTCON
	mov		r1, #0
	str		r1, [r0]

	;------------------------
	; EBI configuration

;	ldr		r0, =EBICON			; EBI
;	ldr		r1, =EBICON_VAL		; Refer s3c2450.inc
;	str		r1, [r0]

	;-------------------------
	; Configure GPA data High
	ldr		r0, = GPACDH
	ldr		r1, = 0xAA8A
	str		r1, [r0]

	;------------------------
	; GIPO configuration for LED

	ldr		r0, =GPFCON
	ldr		r1, =0x5500
	str		r1, [r0]

	;------------------------
	; Interrupt configuration

	[ BSP_TYPE = BSP_SMDK2443 	
		ldr		r0, =INTMSK			; mask all first-level interrupts.
		ldr		r1, =0xffffffff
		str		r1, [r0]

		ldr		r0, =INTSUBMSK		; mask all second-level interrupts.
		ldr		r1, =0x1fffffff
		str		r1, [r0]

		ldr		r0, = INTMOD			; set all interrupt as IRQ
		mov		r1, #0x0
		str		r1, [r0]

	]
	[ BSP_TYPE = BSP_SMDK2450 
	    ldr	r0, =INTMSK1      ; mask all first-level interrupts.
	    ldr	r1, =0xffffffff
	    str	r1, [r0]

	    ldr	r0, =INTMSK2      ; mask all first-level interrupts.
	    ldr	r1, =0xffffffff
	    str	r1, [r0]

	    ldr	r0, =INTSUBMSK   ; mask all second-level interrupts.
	    ldr	r1, =0x1fffffff
	    str	r1, [r0]

	    ldr r0, = INTMOD1
	    mov r1, #0x0			; set all interrupt as IRQ
	    str r1, [r0]

	    ldr r0, = INTMOD2
	    mov r1, #0x0			; set all interrupt as IRQ
	    str r1, [r0]
	]

		]

	[BSP_TYPE = BSP_SMDK2443 
	LED_ON	0xa
	]

		[ {FALSE}

	;------------------------
	; Clock configuration

	ldr		r0, =CLKDIV0			; Set Clock Divider
	ldr		r1, [r0]
	bic		r1, r1, #0x37			; clear HCLKDIV, PREDIV, PCLKDIV
	bic		r1, r1, #(0xf<<9)		; clear ARMCLKDIV
	ldr		r2, =((Startup_ARMCLKdiv<<9)+(Startup_PREdiv<<4)+(Startup_PCLKdiv<<2)+(Startup_HCLKdiv))
	orr		r1, r1, r2
	str		r1, [r0]

	ldr		r0, =LOCKCON0		; Set lock time of MPLL. added by junon
	mov		r1, #0xe10			; Fin = 12MHz -0x800, 16.9844MHz -0xA00
	str		r1, [r0]

	ldr		r0,=LOCKCON1		;	Set lock time of EPLL. added by junon
	mov		r1,#0x800			;	Fin = 12MHz - 0x800, 16.9844MHz - 0xA00
	str		r1,[r0]

	ldr		r0, =MPLLCON			; Set MPLL
	[ BSP_TYPE = BSP_SMDK2443 	
	ldr		r1,=((0<<24)+(Startup_Mdiv<<16)+(Startup_Pdiv<<8)+(Startup_Sdiv))
	]
	[ BSP_TYPE = BSP_SMDK2450 
	ldr		r1,=((0<<24)+(Startup_Mdiv<<14)+(Startup_Pdiv<<5)+(Startup_Sdiv))
	]
	str		r1, [r0]

  	ldr		r0,=EPLLCON			;	Set EPLL
	ldr		r1,=((0<<24)+(Startup_EMdiv<<16)+(Startup_EPdiv<<8)+(Startup_ESdiv))
	str		r1,[r0]

	ldr		r0, =CLKSRC			; Select MPLL clock out for SYSCLK
	ldr		r1, [r0]
	orr		r1, r1, #0x50
	str		r1, [r0]

	;----------------------------
	; MMU set Asynchonous Bus Mode

	bl		MMU_SetAsyncBusMode

   	;----------------------------
	; Memory Controller initialize

;	bl		InitMEM

   	;----------------------------
	; SMC initialize

	bl		InitSSMC

		]

	;----------------------------
	;  Copy boot loader to memory

	ands		r9, pc, #0xFF000000		; see if we are in flash or in ram
	bne		%F20					; go ahead if we are already in ram

        ; This is the loop that perform copying.
;        ldr     r0, = 0x38000           ; offset into the RAM
;        add     r0, r0, #PHYBASE        ; add physical base
;        mov     r1, r0                  ; (r1) copy destination
;        ldr     r2, =0x0                ; (r2) flash started at physical address 0
;        ldr     r3, =0x10000            ; counter (0x40000/4)
;10      ldr     r4, [r2], #4
;        str     r4, [r1], #4
;        subs    r3, r3, #1
;        bne     %b10

;        ; Restart from the RAM position after copying.
;        mov pc, r0
;        nop
;        nop
;        nop

;        ; Shouldn't get here.
;        b       .

	INCLUDE oemaddrtab_cfg.inc

	;----------------------------
	; Compute physical address of the OEMAddressTable.

20
	add		r11, pc, #g_oalAddressTable -(. + 8)
	ldr		r10, =PTs							; (r10) = 1st level page table

	;----------------------------
	; Setup 1st level page table (using section descriptor)
	; Fill in first level page table entries to create "un-mapped" regions
	; from the contents of the MemoryMap array.
	;
	; (r10) = 1st level page table
	; (r11) = ptr to MemoryMap array

	add		r10, r10, #0x2000		; (r10) = ptr to 1st PTE for "unmapped space"
	mov		r0, #0x0E			; (r0) = PTE for 0: 1MB cachable bufferable
	orr		r0, r0, #0x400		; set kernel r/w permission
25
	mov		r1, r11				; (r1) = ptr to MemoryMap array

30
	ldr		r2, [r1], #4			; (r2) = virtual address to map Bank at
	ldr		r3, [r1], #4			; (r3) = physical address to map from
	ldr		r4, [r1], #4			; (r4) = num MB to map

	cmp		r4, #0				; End of table?
	beq		%F40

	ldr		r5, =0x1FF00000
	and		r2, r2, r5				; VA needs 512MB, 1MB aligned.

	ldr		r5, =0xFFF00000
	and		r3, r3, r5				; PA needs 4GB, 1MB aligned.

	add		r2, r10, r2, LSR #18
	add		r0, r0, r3				; (r0) = PTE for next physical page

35
	str		r0, [r2], #4
	add		r0, r0, #0x00100000	; (r0) = PTE for next physical page
	sub		r4, r4, #1			; Decrement number of MB left
	cmp		r4, #0
	bne		%B35				; Map next MB

	bic		r0, r0, #0xF0000000	; Clear Section Base Address Field
	bic		r0, r0, #0x0FF00000	; Clear Section Base Address Field
	b		%B30				; Get next element

40
	tst		r0, #8
	bic		r0, r0, #0x0C			; clear cachable & bufferable bits in PTE
	add		r10, r10, #0x0800		; (r10) = ptr to 1st PTE for "unmapped uncached space"
	bne		%B25				; go setup PTEs for uncached space
	sub		r10, r10, #0x3000		; (r10) = restore address of 1st level page table

	;----------------------------------------------
	; Setup mmu to map (VA == 0) to (PA == 0x30000000).

	; cached area
	ldr		r0, =PTs				; PTE entry for VA = 0
	ldr		r1, =0x3000040E		; cache/unbuffer/rw, PA base == 0x30000000
	str		r1, [r0]

	; uncached area.
	add		r0, r0, #0x0800		; PTE entry for VA = 0x0200.0000 , uncached
	ldr		r1, =0x30000402		; uncache/unbuffer/rw, base == 0x30000000
	str		r1, [r0]

	; Comment:
	; The following loop is to direct map RAM VA == PA. i.e.
	;   VA == 0x30XXXXXX => PA == 0x30XXXXXX for S3C2400
	; Fill in 8 entries to have a direct mapping for DRAM

	ldr		r10, =PTs			; restore address of 1st level page table
	ldr		r0,  =PHYBASE

	add		r10, r10, #(0x3000 / 4)	; (r10) = ptr to 1st PTE for 0x30000000

	add		r0, r0, #0x1E			; 1MB cachable bufferable
	orr		r0, r0, #0x400		; set kernel r/w permission
	mov		r1, #0
	mov		r3, #64
45
	mov		r2, r1				; (r2) = virtual address to map Bank at
	cmp		r2, #0x20000000:SHR:BANK_SHIFT
	add		r2, r10, r2, LSL #BANK_SHIFT-18
	strlo		r0, [r2]
	add		r0, r0, #0x00100000	; (r0) = PTE for next physical page
	subs		r3, r3, #1
	add		r1, r1, #1
	bgt		%B45

	ldr		r10, =PTs			; (r10) = restore address of 1st level page table

	; The page tables and exception vectors are setup.
	; Initialize the MMU and turn it on.
	mov		r1, #1
	mcr		p15, 0, r1, c3, c0, 0	; setup access to domain 0
	mcr		p15, 0, r10, c2, c0, 0

	mcr		p15, 0, r0, c8, c7, 0	; flush I+D TLBs

	mrc		p15, 0, r1, c1, c0, 0
	orr		r1, r1, #0x0071			; Enable: MMU
	orr		r1, r1, #0x0004		; Enable the cache

	ldr		r0, =VirtualStart

	cmp		r0, #0				; make sure no stall on "mov pc,r0" below
	mcr		p15, 0, r1, c1, c0, 0
	mov		pc, r0				; & jump to new virtual address
	nop

        ; MMU & caches now enabled.
        ;   (r10) = physcial address of 1st level page table

VirtualStart

	[ BSP_TYPE = BSP_SMDK2443
	ldr		sp, =0x8F020000
	]
	[ BSP_TYPE = BSP_SMDK2450
	ldr		sp, =0x83020000
	]
	b		main

	ENTRY_END

	END