startup.s

smdk2416 wince source code/BSP

	add	 r1, r1, #1
	bgt	 %b45

	ldr	 r10, =PTs		   ; (r10) = restore address of 1st level page table

	; The page tables and exception vectors are setup.
	; Initialize the MMU and turn it on.
	mov	 r1, #1
	mcr	 p15, 0, r1, c3, c0, 0   ; setup access to domain 0
	mcr	 p15, 0, r10, c2, c0, 0

	mcr	 p15, 0, r0, c8, c7, 0   ; flush I+D TLBs
	
	mrc     p15,0,r1,c1,c0,0
	
	orr	 r1, r1, #0x0071		 ; Enable: MMU
	orr	 r1, r1, #0x0004	 ; Enable the cache


	ldr	 r0, =VirtualStart

	cmp	 r0, #0		  ; make sure no stall on "mov pc,r0" below
	mcr	 p15, 0, r1, c1, c0, 0

	mov	 pc, r0		  ;  & jump to new virtual address
	nop


	; MMU & caches now enabled.
	;   (r10) = physcial address of 1st level page table
	;


VirtualStart

	mov	 sp, #0x80000000	; have to be modefied. refer oemaddrtab_cfg.inc, DonGo
	add	 sp, sp, #0x30000	; arbitrary initial super-page stack pointer



	b	   main


        ENTRY_END 




	LEAF_ENTRY OALCPUPowerOff

;       1. Push SVC state onto our stack
	stmdb   sp!, {r4-r12}                   
	stmdb   sp!, {lr}

	[ {FALSE}

;       2. Save MMU & CPU Register to RAM
    ldr     r3, =SLEEPDATA_BASE_VIRTUAL     ; base of Sleep mode storage

	ldr     r2, =Awake_address              ; store Virtual return address
	str     r2, [r3], #4

	mrc     p15, 0, r2, c1, c0, 0           ; load r2 with MMU Control
	ldr     r0, =MMU_CTL_MASK               ; mask off the undefined bits
	bic     r2, r2, r0
	str     r2, [r3], #4                    ; store MMU Control data

	mrc     p15, 0, r2, c2, c0, 0           ; load r2 with TTB address.
	ldr     r0, =MMU_TTB_MASK               ; mask off the undefined bits
	bic     r2, r2, r0
	str     r2, [r3], #4                    ; store TTB address

	mrc     p15, 0, r2, c3, c0, 0           ; load r2 with domain access control.
	str     r2, [r3], #4                    ; store domain access control

	str     sp, [r3], #4                    ; store SVC stack pointer

	mrs     r2, spsr
	str     r2, [r3], #4                    ; store SVC status register

	mov     r1, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; Enter FIQ mode, no interrupts
	msr     cpsr, r1
	mrs     r2, spsr
	stmia   r3!, {r2, r8-r12, sp, lr}       ; store the FIQ mode registers

	mov     r1, #Mode_ABT:OR:I_Bit:OR:F_Bit ; Enter ABT mode, no interrupts
	msr     cpsr, r1
	mrs		r0, spsr
	stmia   r3!, {r0, sp, lr}               ; store the ABT mode Registers

	mov     r1, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; Enter IRQ mode, no interrupts
	msr     cpsr, r1
	mrs     r0, spsr
	stmia   r3!, {r0, sp, lr}               ; store the IRQ Mode Registers

	mov     r1, #Mode_UND:OR:I_Bit:OR:F_Bit ; Enter UND mode, no interrupts
	msr     cpsr, r1
	mrs     r0, spsr
	stmia   r3!, {r0, sp, lr}               ; store the UND mode Registers

	mov     r1, #Mode_SYS:OR:I_Bit:OR:F_Bit ; Enter SYS mode, no interrupts
	msr     cpsr, r1
	stmia   r3!, {sp, lr}                   ; store the SYS mode Registers

	mov     r1, #Mode_SVC:OR:I_Bit:OR:F_Bit ; Back to SVC mode, no interrupts
	msr     cpsr, r1

;       3. do Checksum on the Sleepdata
	ldr     r3, =SLEEPDATA_BASE_VIRTUAL	; get pointer to SLEEPDATA
	ldr     r2, =0x0
	ldr     r0, =(SLEEPDATA_SIZE-1)		; get size of data structure (in words)
30
	ldr     r1, [r3], #4
	and     r1, r1, #0x1
	mov     r1, r1, ROR #31
	add     r2, r2, r1
	subs    r0, r0, #1
	bne     %b30

	ldr     r0, =vGPIOBASE
	;;;add		r2, r2, #1				; test checksum of the Sleep data error
	str     r2, [r0, #oGSTATUS3]		; Store in Power Manager Scratch pad register

	ldr     r0, =vGPIOBASE
	ldr     r1, =0x550a
	str     r1, [r0, #oGPFCON]
	
	ldr		r1, =0x30
	str		r1, [r0, #oGPFDAT]	

	]
	
    ldr     r0, =vINTBASE1
    mvn     r2, #0
	str     r2, [r0, #oINTMSK1]
	str     r2, [r0, #oSRCPND1]
	str     r2, [r0, #oINTPND1]

    ldr     r0, =vINTBASE2
    mvn     r2, #0
	str     r2, [r0, #oINTMSK2]
	str     r2, [r0, #oSRCPND2]



;;       5. Cache Flush
;	bl		OALClearUTLB
;	bl		OALFlushICache
;	ldr     r0, = (DCACHE_LINES_PER_SET - 1)    
;	ldr     r1, = (DCACHE_NUM_SETS - 1)    
;	ldr     r2, = DCACHE_SET_INDEX_BIT    
;	ldr     r3, = DCACHE_LINE_SIZE     
;	bl		OALFlushDCache
    
;       6. Setting Wakeup External Interrupt(EINT0,1,2) Mode
	ldr     r0, =vGPIOBASE

	ldr     r1, =0x5502
	str     r1, [r0, #oGPFCON]


	ldr     r4, =vOSCSET
	ldr     r5, =0xffff            
	str     r5, [r4]

	ldr     r4, =vPWRCFG
	ldr     r5, =0x8101
	str     r5, [r4]

	ldr     r4, =vPWRMODE
	ldr     r5, =0x2BED            ; Power Off Mode
	str     r5, [r4]		; Power Off !!
        b .


;;;	LTORG

; This point is called from EBOOT's startup code(MMU is enabled)
;       in this routine, left information(REGs, INTMSK, INTSUBMSK ...)

Awake_address

;       1. Recover CPU Registers

	ldr     r3, =SLEEPDATA_BASE_VIRTUAL		; Sleep mode information data structure
	add     r2, r3, #SleepState_FIQ_SPSR
	mov     r1, #Mode_FIQ:OR:I_Bit:OR:F_Bit		; Enter FIQ mode, no interrupts - also FIQ
	msr     cpsr, r1
	ldr     r0,  [r2], #4
	msr     spsr, r0
	ldr     r8,  [r2], #4
	ldr     r9,  [r2], #4
	ldr     r10, [r2], #4
	ldr     r11, [r2], #4
	ldr     r12, [r2], #4
	ldr     sp,  [r2], #4
	ldr     lr,  [r2], #4

	mov     r1, #Mode_ABT:OR:I_Bit			; Enter ABT mode, no interrupts
	msr     cpsr, r1
	ldr     r0, [r2], #4
	msr     spsr, r0
	ldr     sp, [r2], #4
	ldr     lr, [r2], #4

	mov     r1, #Mode_IRQ:OR:I_Bit			; Enter IRQ mode, no interrupts
	msr     cpsr, r1
	ldr     r0, [r2], #4
	msr     spsr, r0
	ldr     sp, [r2], #4
	ldr     lr, [r2], #4

	mov     r1, #Mode_UND:OR:I_Bit			; Enter UND mode, no interrupts
	msr     cpsr, r1
	ldr     r0, [r2], #4
	msr     spsr, r0
	ldr     sp, [r2], #4
	ldr     lr, [r2], #4

	mov     r1, #Mode_SYS:OR:I_Bit			; Enter SYS mode, no interrupts
	msr     cpsr, r1
	ldr     sp, [r2], #4
	ldr     lr, [r2]

	mov     r1, #Mode_SVC:OR:I_Bit					; Enter SVC mode, no interrupts - FIQ is available
	msr     cpsr, r1
	ldr     r0, [r3, #SleepState_SVC_SPSR]
	msr     spsr, r0

;       2. Recover Last mode's REG's, & go back to caller of OALCPUPowerOff()

	ldr     sp, [r3, #SleepState_SVC_SP]
	ldr     lr, [sp], #4
	ldmia   sp!, {r4-r12}
	mov     pc, lr                          ; and now back to our sponsors

	

InitSSMC

	;Set SSMC Memory parameter control registers : AMD Flash
	ldr		r0,=SMBIDCYR0
	ldr		r1,=IDCY0
	str		r1,[r0]
	
	ldr		r0,=SMBWSTRDR0
	ldr		r1,=WSTRD0
	str		r1,[r0]
	
	ldr		r0,=SMBWSTWRR0
	ldr		r1,=WSTWR0
	str		r1,[r0]
	
	ldr		r0,=SMBWSTOENR0
	ldr		r1,=WSTOEN0
	str		r1,[r0]
	
	ldr		r0,=SMBWSTWENR0
	ldr		r1,=WSTWEN0
	str		r1,[r0]
	
	ldr		r0,=SMBCR0
	ldr		r1,=(SMBCR0_2+SMBCR0_1+SMBCR0_0)
	str		r1,[r0]
	
	ldr		r0,=SMBWSTBRDR0
	ldr		r1,=WSTBRD0
	str		r1,[r0]

	
	ldr		r0,=SMBWSTBRDR0
	ldr		r1,=WSTBRD0
	str		r1,[r0]

	ldr		r0,=SSMCCR
	ldr		r1,=((MemClkRatio<<1)+(SMClockEn<<0))
	str		r1,[r0]
	
	;ldr		r0,=SMBWSTRDR5
	;ldr		r1,=0xe
	;str		r1,[r0]
	
	mov pc, lr

        LTORG

MMU_SetAsyncBusMode

        mrc     p15,0,r0,c1,c0,0
        orr     r0,r0,#R1_nF:OR:R1_iA
        mcr     p15,0,r0,c1,c0,0
        mov 	pc, lr




	[BSP_TYPE = BSP_SMDK2443 
loop_led

	LED_ON	0x3

	ldr r0,=0x800000
10	subs r0, r0, #1
	bne %B10	

	LED_ON	0xC

	ldr r0,=0x800000
12	subs r0, r0, #1
	bne %B12	

	b loop_led

vloop_led

	VLED_ON	0xe

	ldr r0,=0x80000
10	subs r0, r0, #1
	bne %B10	

	VLED_ON	0xf

	ldr r0,=0x80000
12	subs r0, r0, #1
	bne %B12	

	b vloop_led	; Infinite loop
	]

        ENTRY_END 




;------------------------------------------------------------------------------
; Clock Division Change funtion for DVS on S3C2450.
;------------------------------------------------------------------------------

;	LEAF_ENTRY CLKDIV124
;	ldr     r0, = vCLKDIVN
;	ldr     r1, = 0x3		; 0x3 = 1:2:4
;	str     r1, [r0]
;	mov     pc, lr

;	LEAF_ENTRY CLKDIV144
;	ldr     r0, = vCLKDIVN
;	ldr     r1, = 0x4		; 0x4 = 1:4:4
;	str     r1, [r0]
;	mov     pc, lr

;	LEAF_ENTRY CLKDIV136
;	ldr     r0, = vCLKDIVN
;	ldr     r1, = 0x7			; 1:6:12
;	str     r1, [r0]
;	ldr     r0, = vCAMDIVN
;	ldr		r1, [r0]
;	bic		r1, r1, #(0x3<<8)
;	orr		r1, r1, #(0x0<<8)	; 1:3:6
;	str     r1, [r0]	
;	mov     pc, lr

;	LEAF_ENTRY CLKDIV166
;	ldr     r0, = vCAMDIVN
;	ldr		r1, [r0]
;	bic		r1, r1, #(0x3<<8)
;	orr		r1, r1, #(0x1<<8)	; 1:6:12
;	str     r1, [r0]
;	ldr     r0, = vCLKDIVN
;	ldr     r1, = 0x6			; 1:6:6
;	str     r1, [r0]	
;	mov     pc, lr

;	LEAF_ENTRY CLKDIV148
;	ldr     r0, = vCLKDIVN
;	ldr     r1, = 0x5			; 1:8:16
;	ldr     r2, = vCAMDIVN
;	ldr		r3, [r2]
;	bic		r3, r3, #(0x3<<8)
;	orr		r3, r3, #(0x0<<8)	; 1:4:8
;	str     r1, [r0]
;	str     r3, [r2]
;	mov     pc, lr

;	LEAF_ENTRY CLKDIV188
;	ldr     r0, = vCAMDIVN
;	ldr		r1, [r0]
;	bic		r1, r1, #(0x3<<8)
;	orr		r1, r1, #(0x2<<8)	; 1:8:16
;	ldr     r2, = vCLKDIVN
;	ldr     r3, = 0x4			; 1:8:8
;	str     r1, [r0]
;	str     r3, [r2]
;	mov     pc, lr

;	LEAF_ENTRY DVS_ON	
;	ldr		r0, = vCAMDIVN
;	ldr		r1, [r0]
;	orr		r1, r1, #(0x1<<12)	; DVS_EN bit = 1(FCLK = HCLK)
;	str		r1, [r0]
;	mov		pc, lr

;	LEAF_ENTRY DVS_OFF
;	ldr		r0, = vCAMDIVN
;	ldr		r1, [r0]
;	bic		r1, r1, #(0x1<<12)	; DVS_EN bit = 0(FCLK = MPLL clock)
;	str		r1, [r0]
;	mov		pc, lr
	
        END

;------------------------------------------------------------------------------