controlrw.c

来自「utisoftware c code for linux,机卡分离方案。」· C语言 代码 · 共 477 行 · 第 1/2 页

 *-----------------------------------------------------------------------------
 *""FUNC COMMENT END""********************************************************/
U16 ControlNoWrite(U16 Req, U16 Val, U16 Indx, U16 Len)
{
	U16	stat, i;
	
	/* ----- Setup Stage ----- */
	if( SetupStage(Req, Val, Indx, Len) != SACK )
		return SIGN;

	//mdelay(10);
	/* ----- Status Stage ----- */
	for(i=0;i<10;i++)/*Perhaps the card plugged in responses slowly because of its SOC speed. J20051013*/
	{
		stat = StatusStage(CS_WRSS);                    /* Control Write Status Stage */
		if(stat!=SACK)
			mdelay(1);
		else
			break;
	}
	
	return stat;
}


/*""FUNC COMMENT""*************************************************************
 *-----------------------------------------------------------------------------
 * Function		: Control read
 *-----------------------------------------------------------------------------
 * Declaration	: U16 ControlRead(U16 Req, U16 Val, U16 Indx, U16 Len, U8 *Buf)
 *-----------------------------------------------------------------------------
 * Argument		: U16 Req			; bmRequestType & bRequest
 *				: U16 Val			; wValue
 *				: U16 Indx			; wIndex
 *				: U16 Len			; wLength
 *				: U8  *Buf			; Data buffer
 *-----------------------------------------------------------------------------
 * Return		: U16				; SACK : Done
 *				:					; SIGN : Error
 *-----------------------------------------------------------------------------
 * Note			:
 *-----------------------------------------------------------------------------
 *""FUNC COMMENT END""********************************************************/
U16 ControlRead(U16 Req, U16 Val, U16 Indx, U16 Len, U8 *Buf)
{
	U16	stat;
	/* ----- Setup Stage ----- */
	if(SetupStage(Req, Val, Indx, Len) != SACK )
		return SIGN;
	/* ----- Data Stage ----- */
	USB_CLR_PAT(NRDYSTS, NRDY0);
	CR_Start((U32)Len, Buf);

	while( 1 ) {									/* Wait Data End */
		udelay(10);
		if( dtcnt[PIPE0] == 0 )
			break;
		USBRD(NRDYSTS, stat);
		if( (stat & NRDY0) != 0 )
			break;
	}
	USBRD(NRDYSTS, stat);
	if( (stat & NRDY0) != 0 )
		return SIGN;

	/* ----- Status Stage ----- */
	stat = StatusStage(CS_RDSS);					/* Control Read Status Stage */
	return stat;
}

/*""FUNC COMMENT""*************************************************************
 *-----------------------------------------------------------------------------
 * Function		: Control write
 *-----------------------------------------------------------------------------
 * Declaration	: U16 ControlWrite(U16 Req, U16 Val, U16 Indx, U16 Len, U8 *Buf)
 *-----------------------------------------------------------------------------
 * Argument		: U16 Req			; bmRequestType & bRequest
 *				: U16 Val			; wValue
 *				: U16 Indx			; wIndex
 *				: U16 Len			; wLength
 *				: U8  *Buf			; Data buffer
 *-----------------------------------------------------------------------------
 * Return		: U16				; SACK : Done
 *				:					; SIGN : Error
 *-----------------------------------------------------------------------------
 * Note			:
 *-----------------------------------------------------------------------------
 *""FUNC COMMENT END""********************************************************/
U16 ControlWrite(U16 Req, U16 Val, U16 Indx, U16 Len, U8 *Buf)
{
	U16	stat;

	/* ----- Setup Stage ----- */
	if( SetupStage(Req, Val, Indx, Len) != SACK )
		return SIGN;
	/* ----- Data Stage ----- */
	USB_CLR_PAT(NRDYSTS, NRDY0);
	CW_Start((U32)Len, Buf);

	while( 1 ) {									/* Wait Data End */
#if 0
		if( dtcnt[PIPE0] == 0 )
			break;
#endif

	USBRD(BEMPSTS,  stat);
	if ( ((stat & BEMP0) != 0) && (dtcnt[PIPE0] ==0) ) 
	/*if (dtcnt[PIPE0] ==0 )*/
		break;

		USBRD(NRDYSTS, stat);
		if( (stat & NRDY0) != 0 )
			break;
	}
	USBRD(NRDYSTS, stat);
	mdelay(1);
	if( (stat & NRDY0) != 0 )
		return SIGN;

	/* ----- Status Stage ----- */
	stat = StatusStage(CS_WRSS);					/* Control Write Status Stage */
	return stat;
}


/*""FUNC COMMENT""*************************************************************
 *-----------------------------------------------------------------------------
 * Function		: Setup stage
 *-----------------------------------------------------------------------------
 * Declaration	: U16 SetupStage(U16 Req, U16 Val, U16 Indx, U16 Len)
 *-----------------------------------------------------------------------------
 * Argument		: U16 Req			; bmRequestType & bRequest
 *				: U16 Val			; wValue
 *				: U16 Indx			; wIndex
 *				: U16 Len			; wLength
 *-----------------------------------------------------------------------------
 * Return		: U16				; SACK : Done
 *				:					; SIGN : Error
 *-----------------------------------------------------------------------------
 * Note			:
 *-----------------------------------------------------------------------------
 *""FUNC COMMENT END""********************************************************/
U16 SetupStage(U16 Req, U16 Val, U16 Indx, U16 Len)
{
	U16	buffer, i;

	USB_CLR_STS(INTSTS1, (SACK | SIGN));			/* Status Clear */

	USBWR(USBREQ,  Req);
	USBWR(USBVAL,  Val);
	USBWR(USBINDX, Indx);
	USBWR(USBLENG, Len);

	USBWR(DCPCTR,  SUREQ);							/* Send Setup */

	for( i = 0; i < 30000; ++i ) {					/* Wait ACK or SIGN */
		USBRD(INTSTS1, buffer);
		if( buffer & SACK )
			return SACK;							/* ACK */
		else if( buffer & SIGN )
			return SIGN;							/* Ignore */
	}
	return SIGN;
}


/*""FUNC COMMENT""*************************************************************
 *-----------------------------------------------------------------------------
 * Function		: Status stage
 *-----------------------------------------------------------------------------
 * Declaration	: U16 StatusStage(U16 Mode)
 *-----------------------------------------------------------------------------
 * Argument		: U16 Mode			; CS_WRSS : Control write status stage
 *				:					; CS_RDSS : Control read  status stage
 *-----------------------------------------------------------------------------
 * Return		: U16				; SACK : Done
 *				:					; SIGN : Error
 *-----------------------------------------------------------------------------
 * Note			:
 *-----------------------------------------------------------------------------
 *""FUNC COMMENT END""********************************************************/
U16 StatusStage(U16 Mode)
{
	U16	buffer, i;

	USB_CLR_PAT(BRDYENB, BRDY0);
	USB_CLR_PAT(BEMPENB, BEMP0);
	USB_CLR_STS(BRDYSTS, BRDY0);					/* Clear */
	USB_CLR_STS(BEMPSTS, BEMP0);

	USBWR(DCPCTR, SQSET);							/* SQSET=1, PID=NAK */

	if( Mode == CS_WRSS ) 
	{
		/* ----- Control Write Status Stage ----- */
		USB_CLR_PAT(DCPCFG, DIR);					/* DIR=0 */
		USB_MDF_PAT(CFIFOSEL, PIPE0, (ISEL | CURPIPE));	/* ISEL=0, CURPIPE=EP0 */
		USBWR(CFIFOCTR, BCLR);						/* BCLR */
		USBWR(DCPCTR, PID_BUF);						/* PID=BUF */
		
		for( i = 0; i < 300; ++i ) 		{				/* Wait */
			USBRD(NRDYSTS, buffer);
			udelay(10);
			//STTBX_Print(("NRDYSTS register's value = %x\n", buffer));

			USBRD(BRDYSTS, buffer);
			udelay(10);
			//STTBX_Print(("BRDYSTS register's value = %x\n", buffer));

			if( buffer & BRDY0 ) {
/*--------------------------------------*/
				USB_CLR_STS(BRDYSTS, BRDY0);

/*--------------------------------------*/				
				SetEpPid(PIPE0, PID_NAK);
				return SACK;						/* Done */
			}
		}
	}
	else {
		/* ----- Control Read Status Stage ----- */
		USB_SET_PAT(DCPCFG, DIR);					/* DIR=1 */
		USB_MDF_PAT(CFIFOSEL, (ISEL | PIPE0), (ISEL | CURPIPE));	/* ISEL=1, CURPIPE=EP0 */
		USBWR(CFIFOCTR, (BVAL | BCLR));				/* BCLR + BVAL */
		USBWR(DCPCTR, PID_BUF);						/* PID=BUF */

		for( i = 0; i < 30000; ++i ) {				/* Wait */
			USBRD(BEMPSTS, buffer);
			if( buffer & BEMP0 ) {
				
				SetEpPid(PIPE0, PID_NAK);
				return SACK;						/* Done */
			}
		}
	}
	return SIGN;									/* Error */
}