testbench_sc_8bit_updowncounter.cpp

来自「在SystemC下编的fibonicii 的程序」· C++ 代码 · 共 86 行

// All systemc modules should include systemc.h header file
#include <systemc.h>
#include "SC_8bit_UpDownCounter.cpp"

// entry point of the application
int sc_main(int argc,char* argv[])
{
	sc_report_handler::set_actions("/IEEE_Std_1666/deprecated",SC_DO_NOTHING);
	// input ports
	sc_signal<bool>			clock;
	sc_signal<bool>			reset;
	sc_signal<bool>			enable;
	sc_signal<bool>			up_down;
	// output ports
	sc_signal<sc_uint<8>>	counter_out;

	int i = 0;
	// connect the Device Under Test (DUT)
	up_down_counter counter("UP_DOWN_COUNTER");
	// port map : map signals to ports
	counter.clk(clock);
	counter.reset(reset);
	counter.enable(enable);
	counter.up_down(up_down);
	counter.counter_out(counter_out);
	// start simulation here
	sc_start(1);
	// Open VCD file
	sc_trace_file *wf = sc_create_vcd_trace_file("up_down_counter");
	// dump the desired signals
	sc_trace(wf,clock,"clock");
	sc_trace(wf,reset,"reset");
	sc_trace(wf,enable,"enable");
	sc_trace(wf,up_down,"up_down");
	sc_trace(wf,counter_out,"count");

	// initialize all variables
	reset = 0;						// initial value of reset
	enable = 0;						// initial value of enable
	for(i=0;i<5;i++)
	{
		clock = 0;
		sc_start(1);
		clock = 1;
		sc_start(1);
	}
	reset = 1;						//	assert the reset
	cout << "@" << sc_time_stamp() << "Asserting Reset\n" << endl;
	for(i=0;i<10;i++){
		clock = 0;
		sc_start(1);
		clock = 1;
		sc_start(1);
	}
	reset = 0;						// de-assert the reset
	cout << "@" << sc_time_stamp() << "De-Asserting Reset\n" << endl;
	for(i=0;i<5;i++){
		clock = 0;
		sc_start(1);
		clock = 1;
		sc_start(1);
	}
	enable = 1;						// Assert enable
	up_down = 1;					// Assert up_down -> count up
	cout << "@" << sc_time_stamp() << "Asserting Enable\n" << endl;
	cout << "@" << sc_time_stamp() << "Asserting Up_Down -> count up\n" << endl;
	for(i=0;i<20;i++){
		clock = 0;
		sc_start(1);
		clock = 1;
		sc_start(1);
	}
	up_down = 0;					// de-assert up_down -> count down
	cout << "@" << sc_time_stamp() << "Asserting Up_Down -> count up\n" << endl;
	for(i=0;i<10;i++){
		clock = 0;
		sc_start(1);
		clock = 1;
		sc_start(1);
	}
	enable = 0;						// de-assert enable
	cout << "@" << sc_time_stamp() << "De-Asserting Enable\n" << endl;
	cout << "@" << sc_time_stamp() << "Terminating simulation !\n" << endl;
	sc_close_vcd_trace_file(wf);
	return (0);						// terminate simulation
}