📄 boot.s
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;**************************************************************
;
; This an simple implementation of bootloader for S3C4510B
; Hope it is useful to you.
;
; Enjoy it!
;
;**************************************************************
AREA Init, CODE, READONLY
CODE32
; GET snds.s
;/*************************************************************************/
;/* Format of the Program Status Register */
;/*************************************************************************/
;/* */
;/* 31 30 29 28 7 6 5 4 3 2 1 0 */
;/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+ */
;/*| N | Z | C | V | | I | F | T | M4 ~ M0 | */
;/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+ */
;/* */
;/* Processor Mode and Mask */
;/* */
;/*************************************************************************/
;
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
MASK_MODE EQU 0x0000003F
MODE_SVC32 EQU 0x00000013
I_BIT EQU 0x80 ; when I bit is set, IRQ is disabled
F_BIT EQU 0x40 ; when F bit is set, FIQ is disabled
ASIC_BASE EQU 0x03ff0000
;SYSTEM MANAGER REGISTERS
ARM7_SYSCFG EQU (ASIC_BASE+0x0000)
ARM7_CLKCON EQU (ASIC_BASE+0x3000)
ARM7_EXTACON0 EQU (ASIC_BASE+0x3008)
ARM7_EXTACON1 EQU (ASIC_BASE+0x300c)
ARM7_EXTDBWTH EQU (ASIC_BASE+0x3010)
ARM7_ROMCON0 EQU (ASIC_BASE+0x3014)
ARM7_ROMCON1 EQU (ASIC_BASE+0x3018)
ARM7_ROMCON2 EQU (ASIC_BASE+0x301c)
ARM7_ROMCON3 EQU (ASIC_BASE+0x3020)
ARM7_ROMCON4 EQU (ASIC_BASE+0x3024)
ARM7_ROMCON5 EQU (ASIC_BASE+0x3028)
ARM7_DRAMCON0 EQU (ASIC_BASE+0x302c)
ARM7_DRAMCON1 EQU (ASIC_BASE+0x3030)
ARM7_DRAMCON2 EQU (ASIC_BASE+0x3034)
ARM7_DRAMCON3 EQU (ASIC_BASE+0x3038)
ARM7_REFEXTCON EQU (ASIC_BASE+0x303c)
; controller registers
ARM7_INTMODE EQU (ASIC_BASE+0x4000)
ARM7_INTPEND EQU (ASIC_BASE+0x4004)
ARM7_INTMASK EQU (ASIC_BASE+0x4008)
ARM7_INTOFFSET EQU (ASIC_BASE+0x4024)
ARM7_INTPENDTST EQU (ASIC_BASE+0x402c)
ARM7_INTPRI0 EQU (ASIC_BASE+0x400C)
ARM7_INTPRI1 EQU (ASIC_BASE+0x4010)
ARM7_INTPRI2 EQU (ASIC_BASE+0x4014)
ARM7_INTPRI3 EQU (ASIC_BASE+0x4018)
ARM7_INTPRI4 EQU (ASIC_BASE+0x401C)
ARM7_INTPRI5 EQU (ASIC_BASE+0x4020)
ARM7_INTOSET_FIQ EQU (ASIC_BASE+0x4030)
ARM7_INTOSET_IRQ EQU (ASIC_BASE+0x4034)
; I/O Port Interface
ARM7_IOPMOD EQU (ASIC_BASE+0x5000)
ARM7_IOPCON EQU (ASIC_BASE+0x5004)
ARM7_IOPDATA EQU (ASIC_BASE+0x5008)
; IIC Registers
ARM7_IICCON EQU (ASIC_BASE+0xf000)
ARM7_IICBUF EQU (ASIC_BASE+0xf004)
ARM7_IICPS EQU (ASIC_BASE+0xf008)
ARM7_IICCNT EQU (ASIC_BASE+0xf00c)
;/*************************************************************************/
;/* SYSTEM MEMORY CONTROL REGISTER EQU TABLES */
;/*************************************************************************/
;***************Init***************
rEXTDBWTH EQU 0x00003001
rROMCON0 EQU 0x02000060
rROMCON1 EQU 0x60
rROMCON2 EQU 0x60
rROMCON3 EQU 0x60
rROMCON4 EQU 0x60
rROMCON5 EQU 0x60
rSDRAMCON0 EQU 0x12008380
rSDRAMCON1 EQU 0x00
rSDRAMCON2 EQU 0x00
rSDRAMCON3 EQU 0x00
rSREFEXTCON EQU 0xCE278360
;************Memory Remap**************
rEXTDBWTH_R EQU 0x00003001
rROMCON0_R EQU 0x12040060
rROMCON1_R EQU 0x60
rROMCON2_R EQU 0x60
rROMCON3_R EQU 0x60
rROMCON4_R EQU 0x60
rROMCON5_R EQU 0x60
rSDRAMCON0_R EQU 0x10000380
rSDRAMCON1_R EQU 0x00
rSDRAMCON2_R EQU 0x00
rSDRAMCON3_R EQU 0x00
rSREFEXTCON_R EQU 0xCE278360
;/***************************************************************/
ENTRY
start
;Part 1
;***************************************************************
;disable interrupts in CPU and switch to SVC32 mode
MRS r0, cpsr
BIC r0, r0, #MASK_MODE
ORR r0, r0, #MODE_SVC32
ORR r0, r0, #I_BIT
ORR r0, r0, #F_BIT
MSR cpsr_c, r0
LDR r2, =ARM7_INTMASK ;R2->interrupt controller
MVN r1, #0 ;&FFFFFFFF
STR r1, [r2] ;disable all interrupt soucres
LDR r2, =ARM7_INTPEND ;R2->interrupt pend register.
MVN r1, #0 ;&FFFFFFFF
STR r1, [r2] ;clear all interrupt flags.
;Part 2
;****************************************************************
LDR r0, =ARM7_SYSCFG
LDR r1, =0x87ffffA0 ;config SYSCFG
STR r1, [r0] ;Cache & WB disabled
;Part 3
;***************************************************************
; Import some important variables for later use
IMPORT |Image$$RO$$Base|
IMPORT |Image$$RO$$Limit|
IMPORT |Image$$RW$$Base|
IMPORT |Image$$RW$$Limit|
IMPORT |Image$$ZI$$Base|
IMPORT |Image$$ZI$$Limit|
;Part 4
;*****************************************************************
; copy all to RO-Base;with this code , can specify -ro-base 0X9000 or other or default 0x8000 when compile
LDR r0, =|Image$$RO$$Base| ; destination to copy
LDR r1, =|Image$$RO$$Limit|
SUB r1, r1, r0
LDR r2, =|Image$$RW$$Base|
LDR r3, =|Image$$RW$$Limit|
LDR r5, =|Image$$ZI$$Base|
SUB r3, r3, r2
ADD r3, r3, r1 ; lenght of all
MOV r1, #0x8000 ; source to copy
COPYALL
LDR r4, [r1], #4
STR r4, [r0], #4
SUBS r3, r3, #4
BNE COPYALL
; COPYRW
LDR r0, =|Image$$RO$$Limit| ;source to copy
COPYRW
CMP r2, r5
LDRCC r4, [r0], #4
STRCC r4, [r2], #4
BCC COPYRW
; ZI
LDR r0, =|Image$$ZI$$Limit|
MOV r1, #0
DOZI
CMP r5, r0
STRCC r1, [r5], #4
BCC DOZI
;Part 5
;***********************************************************************
;Set stack pointer & jump to c function
IMPORT myloader
IMPORT do_isr
EXPORT irq_handler
; set stack pointer for irq and svc mode
mov r0, #0xd2 ; make irq mode with all irqs disabled
msr cpsr_cxsf, r0
MOV sp, #0x700000
;set up svc stack
mov r0, #0xd3 ; make svc mode with all irqs disabled
msr cpsr_cxsf, r0
LDR sp, =0x800000
; enable IRQ when in svc mode
MOV r0, #Mode_SVC:OR:F_BIT
MSR cpsr_c, r0
LDR pc, =myloader
; irq handler
irq_handler
SUB lr, lr, #4
STMFD sp!, {r0-r12, lr} ; push r0-r12 register file and lr( pc return address )
MRS r4, spsr
STMFD sp!, {r4} ; push current spsr_cxsf_irq ( =cpsr_svc )
BL do_isr ; goto C handler
; return from irq
LDMFD sp!, {r4} ; get cpsr_svc from stack
MSR spsr_cxsf, r4 ; prepare spsr_cxsf to return svc mode
LDMFD sp!, {r0-r12, pc}^ ; recover r0-r12 and pc from stack, cpsr also
END
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