clock.map.qmsg

一些Verilog学习程序A

{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "sec\[1\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"sec\[1\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "sec\[0\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"sec\[0\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(161) " "Warning (10230): Verilog HDL assignment warning at clock.v(161): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 161 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(162) " "Warning (10230): Verilog HDL assignment warning at clock.v(162): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 162 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "num1\[1\] data_in GND " "Warning: Reduced register \"num1\[1\]\" with stuck data_in port to stuck value GND" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 70 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "num2\[1\] data_in GND " "Warning: Reduced register \"num2\[1\]\" with stuck data_in port to stuck value GND" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 79 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "num3\[1\] data_in GND " "Warning: Reduced register \"num3\[1\]\" with stuck data_in port to stuck value GND" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "num4\[1\] data_in GND " "Warning: Reduced register \"num4\[1\]\" with stuck data_in port to stuck value GND" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 95 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "fm\[0\] fm\[1\] " "Info: Duplicate register \"fm\[0\]\" merged to single register \"fm\[1\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 46 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "clk_2Hz sound\[0\] " "Info: Duplicate register \"clk_2Hz\" merged to single register \"sound\[0\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 29 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "hour\[0\]\$latch " "Warning: Latch hour\[0\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal m\[0\]" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "hour\[1\]\$latch " "Warning: Latch hour\[1\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal m\[0\]" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "hour\[2\]\$latch " "Warning: Latch hour\[2\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal m\[0\]" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "hour\[3\]\$latch " "Warning: Latch hour\[3\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal m\[0\]" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "hour\[4\]\$latch " "Warning: Latch hour\[4\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal m\[0\]" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "hour\[5\]\$latch " "Warning: Latch hour\[5\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal m\[0\]" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "hour\[6\]\$latch " "Warning: Latch hour\[6\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal m\[0\]" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "hour\[7\]\$latch " "Warning: Latch hour\[7\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal m\[0\]" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "min\[0\]\$latch " "Warning: Latch min\[0\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal m\[0\]" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "min\[1\]\$latch " "Warning: Latch min\[1\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal m\[0\]" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "min\[2\]\$latch " "Warning: Latch min\[2\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal m\[0\]" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "min\[3\]\$latch " "Warning: Latch min\[3\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal m\[0\]" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "min\[4\]\$latch " "Warning: Latch min\[4\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal m\[0\]" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "min\[5\]\$latch " "Warning: Latch min\[5\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal m\[0\]" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "min\[6\]\$latch " "Warning: Latch min\[6\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal m\[0\]" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "min\[7\]\$latch " "Warning: Latch min\[7\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal m\[0\]" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "always15_433 " "Warning: Latch always15_433 has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA m\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal m\[0\]" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "206 " "Info: Implemented 206 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "28 " "Info: Implemented 28 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "173 " "Info: Implemented 173 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 68 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 68 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 15 23:11:09 2009 " "Info: Processing ended: Sat Aug 15 23:11:09 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}