clock.map.qmsg

一些Verilog学习程序A

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(138) " "Warning (10230): Verilog HDL assignment warning at clock.v(138): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 138 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(139) " "Warning (10230): Verilog HDL assignment warning at clock.v(139): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 139 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(143) " "Warning (10230): Verilog HDL assignment warning at clock.v(143): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 143 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(144) " "Warning (10230): Verilog HDL assignment warning at clock.v(144): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 144 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "clock.v(152) " "Warning (10270): Verilog HDL statement warning at clock.v(152): incomplete Case Statement has no default case item" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "hour clock.v(152) " "Warning (10240): Verilog HDL Always Construct warning at clock.v(152): inferring latch(es) for variable \"hour\", which holds its previous value in one or more paths through the always construct" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "hour\[7\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"hour\[7\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "hour\[6\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"hour\[6\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "hour\[5\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"hour\[5\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "hour\[4\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"hour\[4\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "hour\[3\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"hour\[3\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "hour\[2\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"hour\[2\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "hour\[1\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"hour\[1\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "hour\[0\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"hour\[0\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "min clock.v(152) " "Warning (10240): Verilog HDL Always Construct warning at clock.v(152): inferring latch(es) for variable \"min\", which holds its previous value in one or more paths through the always construct" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "min\[7\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"min\[7\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "min\[6\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"min\[6\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "min\[5\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"min\[5\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "min\[4\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"min\[4\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "min\[3\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"min\[3\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "min\[2\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"min\[2\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "min\[1\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"min\[1\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "min\[0\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"min\[0\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "sec clock.v(152) " "Warning (10240): Verilog HDL Always Construct warning at clock.v(152): inferring latch(es) for variable \"sec\", which holds its previous value in one or more paths through the always construct" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "sec\[7\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"sec\[7\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "sec\[6\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"sec\[6\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "sec\[5\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"sec\[5\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "sec\[4\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"sec\[4\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "sec\[3\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"sec\[3\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "sec\[2\] clock.v(152) " "Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for \"sec\[2\]\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}