clock.map.qmsg

一些Verilog学习程序A

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 15 23:11:05 2009 " "Info: Processing started: Sat Aug 15 23:11:05 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clock.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 20 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock " "Info: Elaborating entity \"clock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 clock.v(38) " "Warning (10230): Verilog HDL assignment warning at clock.v(38): truncated value with size 32 to match size of target (2)" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 clock.v(44) " "Warning (10230): Verilog HDL assignment warning at clock.v(44): truncated value with size 32 to match size of target (2)" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "clock.v(49) " "Info (10264): Verilog HDL Case Statement information at clock.v(49): all case item expressions in this case statement are onehot" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 49 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "count1 clock.v(67) " "Warning (10240): Verilog HDL Always Construct warning at clock.v(67): inferring latch(es) for variable \"count1\", which holds its previous value in one or more paths through the always construct" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 67 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "count1 clock.v(50) " "Info (10041): Verilog HDL or VHDL info at clock.v(50): inferred latch for \"count1\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 50 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "counta clock.v(67) " "Warning (10240): Verilog HDL Always Construct warning at clock.v(67): inferring latch(es) for variable \"counta\", which holds its previous value in one or more paths through the always construct" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 67 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "counta clock.v(50) " "Info (10041): Verilog HDL or VHDL info at clock.v(50): inferred latch for \"counta\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 50 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "count2 clock.v(67) " "Warning (10240): Verilog HDL Always Construct warning at clock.v(67): inferring latch(es) for variable \"count2\", which holds its previous value in one or more paths through the always construct" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 67 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "count2 clock.v(57) " "Info (10041): Verilog HDL or VHDL info at clock.v(57): inferred latch for \"count2\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 57 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "countb clock.v(67) " "Warning (10240): Verilog HDL Always Construct warning at clock.v(67): inferring latch(es) for variable \"countb\", which holds its previous value in one or more paths through the always construct" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 67 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "countb clock.v(57) " "Info (10041): Verilog HDL or VHDL info at clock.v(57): inferred latch for \"countb\"" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 57 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 clock.v(73) " "Warning (10230): Verilog HDL assignment warning at clock.v(73): truncated value with size 32 to match size of target (2)" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 73 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 clock.v(82) " "Warning (10230): Verilog HDL assignment warning at clock.v(82): truncated value with size 32 to match size of target (2)" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 82 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 clock.v(90) " "Warning (10230): Verilog HDL assignment warning at clock.v(90): truncated value with size 32 to match size of target (2)" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 90 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 clock.v(98) " "Warning (10230): Verilog HDL assignment warning at clock.v(98): truncated value with size 32 to match size of target (2)" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 98 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 clock.v(101) " "Warning (10230): Verilog HDL assignment warning at clock.v(101): truncated value with size 2 to match size of target (1)" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 101 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 clock.v(102) " "Warning (10230): Verilog HDL assignment warning at clock.v(102): truncated value with size 2 to match size of target (1)" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 102 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 clock.v(103) " "Warning (10230): Verilog HDL assignment warning at clock.v(103): truncated value with size 2 to match size of target (1)" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 103 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 clock.v(104) " "Warning (10230): Verilog HDL assignment warning at clock.v(104): truncated value with size 2 to match size of target (1)" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 104 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(113) " "Warning (10230): Verilog HDL assignment warning at clock.v(113): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 113 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(114) " "Warning (10230): Verilog HDL assignment warning at clock.v(114): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 114 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(124) " "Warning (10230): Verilog HDL assignment warning at clock.v(124): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 124 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(125) " "Warning (10230): Verilog HDL assignment warning at clock.v(125): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 125 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(133) " "Warning (10230): Verilog HDL assignment warning at clock.v(133): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 133 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(134) " "Warning (10230): Verilog HDL assignment warning at clock.v(134): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 134 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}