clock.tan.qmsg

一些Verilog学习程序A

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "turn register hour1\[3\] register hour1\[5\] 96.24 MHz 10.391 ns Internal " "Info: Clock \"turn\" has Internal fmax of 96.24 MHz between source register \"hour1\[3\]\" and destination register \"hour1\[5\]\" (period= 10.391 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.636 ns + Longest register register " "Info: + Longest register to register delay is 3.636 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns hour1\[3\] 1 REG LCFF_X22_Y6_N25 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y6_N25; Fanout = 5; REG Node = 'hour1\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { hour1[3] } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.483 ns) + CELL(0.646 ns) 1.129 ns Equal9~96 2 COMB LCCOMB_X22_Y6_N12 3 " "Info: 2: + IC(0.483 ns) + CELL(0.646 ns) = 1.129 ns; Loc. = LCCOMB_X22_Y6_N12; Fanout = 3; COMB Node = 'Equal9~96'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.129 ns" { hour1[3] Equal9~96 } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 132 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.409 ns) + CELL(0.735 ns) 2.273 ns Add10~49 3 COMB LCCOMB_X22_Y6_N14 2 " "Info: 3: + IC(0.409 ns) + CELL(0.735 ns) = 2.273 ns; Loc. = LCCOMB_X22_Y6_N14; Fanout = 2; COMB Node = 'Add10~49'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.144 ns" { Equal9~96 Add10~49 } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 2.779 ns Add10~50 4 COMB LCCOMB_X22_Y6_N16 1 " "Info: 4: + IC(0.000 ns) + CELL(0.506 ns) = 2.779 ns; Loc. = LCCOMB_X22_Y6_N16; Fanout = 1; COMB Node = 'Add10~50'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.506 ns" { Add10~49 Add10~50 } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.379 ns) + CELL(0.370 ns) 3.528 ns hour1~196 5 COMB LCCOMB_X22_Y6_N22 1 " "Info: 5: + IC(0.379 ns) + CELL(0.370 ns) = 3.528 ns; Loc. = LCCOMB_X22_Y6_N22; Fanout = 1; COMB Node = 'hour1~196'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.749 ns" { Add10~50 hour1~196 } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.636 ns hour1\[5\] 6 REG LCFF_X22_Y6_N23 5 " "Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 3.636 ns; Loc. = LCFF_X22_Y6_N23; Fanout = 5; REG Node = 'hour1\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { hour1~196 hour1[5] } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.365 ns ( 65.04 % ) " "Info: Total cell delay = 2.365 ns ( 65.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.271 ns ( 34.96 % ) " "Info: Total interconnect delay = 1.271 ns ( 34.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.636 ns" { hour1[3] Equal9~96 Add10~49 Add10~50 hour1~196 hour1[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.636 ns" { hour1[3] Equal9~96 Add10~49 Add10~50 hour1~196 hour1[5] } { 0.000ns 0.483ns 0.409ns 0.000ns 0.379ns 0.000ns } { 0.000ns 0.646ns 0.735ns 0.506ns 0.370ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-6.491 ns - Smallest " "Info: - Smallest clock skew is -6.491 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "turn destination 12.655 ns + Shortest register " "Info: + Shortest clock path from clock \"turn\" to destination register is 12.655 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns turn 1 CLK PIN_24 3 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_24; Fanout = 3; CLK Node = 'turn'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { turn } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.688 ns) + CELL(0.970 ns) 8.603 ns fm\[1\] 2 REG LCFF_X25_Y7_N31 7 " "Info: 2: + IC(6.688 ns) + CELL(0.970 ns) = 8.603 ns; Loc. = LCFF_X25_Y7_N31; Fanout = 7; REG Node = 'fm\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.658 ns" { turn fm[1] } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.472 ns) + CELL(0.206 ns) 9.281 ns counta 3 REG LCCOMB_X25_Y7_N18 4 " "Info: 3: + IC(0.472 ns) + CELL(0.206 ns) = 9.281 ns; Loc. = LCCOMB_X25_Y7_N18; Fanout = 4; REG Node = 'counta'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.678 ns" { fm[1] counta } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.683 ns) + CELL(0.206 ns) 10.170 ns cta~69 4 COMB LCCOMB_X26_Y7_N16 1 " "Info: 4: + IC(0.683 ns) + CELL(0.206 ns) = 10.170 ns; Loc. = LCCOMB_X26_Y7_N16; Fanout = 1; COMB Node = 'cta~69'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.889 ns" { counta cta~69 } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.000 ns) 11.162 ns cta~69clkctrl 5 COMB CLKCTRL_G7 8 " "Info: 5: + IC(0.992 ns) + CELL(0.000 ns) = 11.162 ns; Loc. = CLKCTRL_G7; Fanout = 8; COMB Node = 'cta~69clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.992 ns" { cta~69 cta~69clkctrl } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.827 ns) + CELL(0.666 ns) 12.655 ns hour1\[5\] 6 REG LCFF_X22_Y6_N23 5 " "Info: 6: + IC(0.827 ns) + CELL(0.666 ns) = 12.655 ns; Loc. = LCFF_X22_Y6_N23; Fanout = 5; REG Node = 'hour1\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.493 ns" { cta~69clkctrl hour1[5] } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.993 ns ( 23.65 % ) " "Info: Total cell delay = 2.993 ns ( 23.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.662 ns ( 76.35 % ) " "Info: Total interconnect delay = 9.662 ns ( 76.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.655 ns" { turn fm[1] counta cta~69 cta~69clkctrl hour1[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.655 ns" { turn turn~combout fm[1] counta cta~69 cta~69clkctrl hour1[5] } { 0.000ns 0.000ns 6.688ns 0.472ns 0.683ns 0.992ns 0.827ns } { 0.000ns 0.945ns 0.970ns 0.206ns 0.206ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "turn source 19.146 ns - Longest register " "Info: - Longest clock path from clock \"turn\" to source register is 19.146 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns turn 1 CLK PIN_24 3 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_24; Fanout = 3; CLK Node = 'turn'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { turn } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.688 ns) + CELL(0.970 ns) 8.603 ns fm\[1\] 2 REG LCFF_X25_Y7_N31 7 " "Info: 2: + IC(6.688 ns) + CELL(0.970 ns) = 8.603 ns; Loc. = LCFF_X25_Y7_N31; Fanout = 7; REG Node = 'fm\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.658 ns" { turn fm[1] } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.469 ns) + CELL(0.206 ns) 9.278 ns count1 3 REG LCCOMB_X25_Y7_N12 4 " "Info: 3: + IC(0.469 ns) + CELL(0.206 ns) = 9.278 ns; Loc. = LCCOMB_X25_Y7_N12; Fanout = 4; REG Node = 'count1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.675 ns" { fm[1] count1 } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.411 ns) + CELL(0.650 ns) 10.339 ns ct1~69 4 COMB LCCOMB_X25_Y7_N14 1 " "Info: 4: + IC(0.411 ns) + CELL(0.650 ns) = 10.339 ns; Loc. = LCCOMB_X25_Y7_N14; Fanout = 1; COMB Node = 'ct1~69'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.061 ns" { count1 ct1~69 } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.385 ns) + CELL(0.000 ns) 12.724 ns ct1~69clkctrl 5 COMB CLKCTRL_G0 9 " "Info: 5: + IC(2.385 ns) + CELL(0.000 ns) = 12.724 ns; Loc. = CLKCTRL_G0; Fanout = 9; COMB Node = 'ct1~69clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.385 ns" { ct1~69 ct1~69clkctrl } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.840 ns) + CELL(0.970 ns) 14.534 ns hclk 6 REG LCFF_X22_Y8_N19 1 " "Info: 6: + IC(0.840 ns) + CELL(0.970 ns) = 14.534 ns; Loc. = LCFF_X22_Y8_N19; Fanout = 1; REG Node = 'hclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.810 ns" { ct1~69clkctrl hclk } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.477 ns) + CELL(0.650 ns) 16.661 ns cta~69 7 COMB LCCOMB_X26_Y7_N16 1 " "Info: 7: + IC(1.477 ns) + CELL(0.650 ns) = 16.661 ns; Loc. = LCCOMB_X26_Y7_N16; Fanout = 1; COMB Node = 'cta~69'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.127 ns" { hclk cta~69 } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.000 ns) 17.653 ns cta~69clkctrl 8 COMB CLKCTRL_G7 8 " "Info: 8: + IC(0.992 ns) + CELL(0.000 ns) = 17.653 ns; Loc. = CLKCTRL_G7; Fanout = 8; COMB Node = 'cta~69clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.992 ns" { cta~69 cta~69clkctrl } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.827 ns) + CELL(0.666 ns) 19.146 ns hour1\[3\] 9 REG LCFF_X22_Y6_N25 5 " "Info: 9: + IC(0.827 ns) + CELL(0.666 ns) = 19.146 ns; Loc. = LCFF_X22_Y6_N25; Fanout = 5; REG Node = 'hour1\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.493 ns" { cta~69clkctrl hour1[3] } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.057 ns ( 26.41 % ) " "Info: Total cell delay = 5.057 ns ( 26.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "14.089 ns ( 73.59 % ) " "Info: Total interconnect delay = 14.089 ns ( 73.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.146 ns" { turn fm[1] count1 ct1~69 ct1~69clkctrl hclk cta~69 cta~69clkctrl hour1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "19.146 ns" { turn turn~combout fm[1] count1 ct1~69 ct1~69clkctrl hclk cta~69 cta~69clkctrl hour1[3] } { 0.000ns 0.000ns 6.688ns 0.469ns 0.411ns 2.385ns 0.840ns 1.477ns 0.992ns 0.827ns } { 0.000ns 0.945ns 0.970ns 0.206ns 0.650ns 0.000ns 0.970ns 0.650ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.655 ns" { turn fm[1] counta cta~69 cta~69clkctrl hour1[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.655 ns" { turn turn~combout fm[1] counta cta~69 cta~69clkctrl hour1[5] } { 0.000ns 0.000ns 6.688ns 0.472ns 0.683ns 0.992ns 0.827ns } { 0.000ns 0.945ns 0.970ns 0.206ns 0.206ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Flo