clock.tan.qmsg

一些Verilog学习程序A

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register hour1\[3\] register hour1\[5\] 68.5 MHz 14.598 ns Internal " "Info: Clock \"clk\" has Internal fmax of 68.5 MHz between source register \"hour1\[3\]\" and destination register \"hour1\[5\]\" (period= 14.598 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.636 ns + Longest register register " "Info: + Longest register to register delay is 3.636 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns hour1\[3\] 1 REG LCFF_X22_Y6_N25 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y6_N25; Fanout = 5; REG Node = 'hour1\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { hour1[3] } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.483 ns) + CELL(0.646 ns) 1.129 ns Equal9~96 2 COMB LCCOMB_X22_Y6_N12 3 " "Info: 2: + IC(0.483 ns) + CELL(0.646 ns) = 1.129 ns; Loc. = LCCOMB_X22_Y6_N12; Fanout = 3; COMB Node = 'Equal9~96'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.129 ns" { hour1[3] Equal9~96 } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 132 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.409 ns) + CELL(0.735 ns) 2.273 ns Add10~49 3 COMB LCCOMB_X22_Y6_N14 2 " "Info: 3: + IC(0.409 ns) + CELL(0.735 ns) = 2.273 ns; Loc. = LCCOMB_X22_Y6_N14; Fanout = 2; COMB Node = 'Add10~49'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.144 ns" { Equal9~96 Add10~49 } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 2.779 ns Add10~50 4 COMB LCCOMB_X22_Y6_N16 1 " "Info: 4: + IC(0.000 ns) + CELL(0.506 ns) = 2.779 ns; Loc. = LCCOMB_X22_Y6_N16; Fanout = 1; COMB Node = 'Add10~50'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.506 ns" { Add10~49 Add10~50 } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.379 ns) + CELL(0.370 ns) 3.528 ns hour1~196 5 COMB LCCOMB_X22_Y6_N22 1 " "Info: 5: + IC(0.379 ns) + CELL(0.370 ns) = 3.528 ns; Loc. = LCCOMB_X22_Y6_N22; Fanout = 1; COMB Node = 'hour1~196'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.749 ns" { Add10~50 hour1~196 } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.636 ns hour1\[5\] 6 REG LCFF_X22_Y6_N23 5 " "Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 3.636 ns; Loc. = LCFF_X22_Y6_N23; Fanout = 5; REG Node = 'hour1\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { hour1~196 hour1[5] } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.365 ns ( 65.04 % ) " "Info: Total cell delay = 2.365 ns ( 65.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.271 ns ( 34.96 % ) " "Info: Total interconnect delay = 1.271 ns ( 34.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.636 ns" { hour1[3] Equal9~96 Add10~49 Add10~50 hour1~196 hour1[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.636 ns" { hour1[3] Equal9~96 Add10~49 Add10~50 hour1~196 hour1[5] } { 0.000ns 0.483ns 0.409ns 0.000ns 0.379ns 0.000ns } { 0.000ns 0.646ns 0.735ns 0.506ns 0.370ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-10.698 ns - Smallest " "Info: - Smallest clock skew is -10.698 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.920 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.920 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_17 6 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns clk~clkctrl 2 COMB CLKCTRL_G2 15 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 15; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.829 ns) + CELL(0.970 ns) 3.042 ns num4\[0\] 3 REG LCFF_X26_Y7_N17 1 " "Info: 3: + IC(0.829 ns) + CELL(0.970 ns) = 3.042 ns; Loc. = LCFF_X26_Y7_N17; Fanout = 1; REG Node = 'num4\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.799 ns" { clk~clkctrl num4[0] } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 95 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.393 ns) 3.435 ns cta~69 4 COMB LCCOMB_X26_Y7_N16 1 " "Info: 4: + IC(0.000 ns) + CELL(0.393 ns) = 3.435 ns; Loc. = LCCOMB_X26_Y7_N16; Fanout = 1; COMB Node = 'cta~69'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.393 ns" { num4[0] cta~69 } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.000 ns) 4.427 ns cta~69clkctrl 5 COMB CLKCTRL_G7 8 " "Info: 5: + IC(0.992 ns) + CELL(0.000 ns) = 4.427 ns; Loc. = CLKCTRL_G7; Fanout = 8; COMB Node = 'cta~69clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.992 ns" { cta~69 cta~69clkctrl } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.827 ns) + CELL(0.666 ns) 5.920 ns hour1\[5\] 6 REG LCFF_X22_Y6_N23 5 " "Info: 6: + IC(0.827 ns) + CELL(0.666 ns) = 5.920 ns; Loc. = LCFF_X22_Y6_N23; Fanout = 5; REG Node = 'hour1\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.493 ns" { cta~69clkctrl hour1[5] } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.129 ns ( 52.85 % ) " "Info: Total cell delay = 3.129 ns ( 52.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.791 ns ( 47.15 % ) " "Info: Total interconnect delay = 2.791 ns ( 47.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.920 ns" { clk clk~clkctrl num4[0] cta~69 cta~69clkctrl hour1[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.920 ns" { clk clk~combout clk~clkctrl num4[0] cta~69 cta~69clkctrl hour1[5] } { 0.000ns 0.000ns 0.143ns 0.829ns 0.000ns 0.992ns 0.827ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.393ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 16.618 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 16.618 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_17 6 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.243 ns clk~clkctrl 2 COMB CLKCTRL_G2 15 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 15; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.829 ns) + CELL(0.970 ns) 3.042 ns sound\[0\] 3 REG LCFF_X27_Y7_N13 4 " "Info: 3: + IC(0.829 ns) + CELL(0.970 ns) = 3.042 ns; Loc. = LCFF_X27_Y7_N13; Fanout = 4; REG Node = 'sound\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.799 ns" { clk~clkctrl sound[0] } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.970 ns) 4.406 ns clk_1Hz 4 REG LCFF_X27_Y7_N31 2 " "Info: 4: + IC(0.394 ns) + CELL(0.970 ns) = 4.406 ns; Loc. = LCFF_X27_Y7_N31; Fanout = 2; REG Node = 'clk_1Hz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.364 ns" { sound[0] clk_1Hz } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.757 ns) + CELL(0.000 ns) 5.163 ns clk_1Hz~clkctrl 5 COMB CLKCTRL_G5 9 " "Info: 5: + IC(0.757 ns) + CELL(0.000 ns) = 5.163 ns; Loc. = CLKCTRL_G5; Fanout = 9; COMB Node = 'clk_1Hz~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.757 ns" { clk_1Hz clk_1Hz~clkctrl } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.834 ns) + CELL(0.970 ns) 6.967 ns minclk 6 REG LCFF_X24_Y7_N15 2 " "Info: 6: + IC(0.834 ns) + CELL(0.970 ns) = 6.967 ns; Loc. = LCFF_X24_Y7_N15; Fanout = 2; REG Node = 'minclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.804 ns" { clk_1Hz~clkctrl minclk } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.638 ns) + CELL(0.206 ns) 7.811 ns ct1~69 7 COMB LCCOMB_X25_Y7_N14 1 " "Info: 7: + IC(0.638 ns) + CELL(0.206 ns) = 7.811 ns; Loc. = LCCOMB_X25_Y7_N14; Fanout = 1; COMB Node = 'ct1~69'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.844 ns" { minclk ct1~69 } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.385 ns) + CELL(0.000 ns) 10.196 ns ct1~69clkctrl 8 COMB CLKCTRL_G0 9 " "Info: 8: + IC(2.385 ns) + CELL(0.000 ns) = 10.196 ns; Loc. = CLKCTRL_G0; Fanout = 9; COMB Node = 'ct1~69clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.385 ns" { ct1~69 ct1~69clkctrl } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.840 ns) + CELL(0.970 ns) 12.006 ns hclk 9 REG LCFF_X22_Y8_N19 1 " "Info: 9: + IC(0.840 ns) + CELL(0.970 ns) = 12.006 ns; Loc. = LCFF_X22_Y8_N19; Fanout = 1; REG Node = 'hclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.810 ns" { ct1~69clkctrl hclk } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.477 ns) + CELL(0.650 ns) 14.133 ns cta~69 10 COMB LCCOMB_X26_Y7_N16 1 " "Info: 10: + IC(1.477 ns) + CELL(0.650 ns) = 14.133 ns; Loc. = LCCOMB_X26_Y7_N16; Fanout = 1; COMB Node = 'cta~69'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.127 ns" { hclk cta~69 } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.000 ns) 15.125 ns cta~69clkctrl 11 COMB CLKCTRL_G7 8 " "Info: 11: + IC(0.992 ns) + CELL(0.000 ns) = 15.125 ns; Loc. = CLKCTRL_G7; Fanout = 8; COMB Node = 'cta~69clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.992 ns" { cta~69 cta~69clkctrl } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.827 ns) + CELL(0.666 ns) 16.618 ns hour1\[3\] 12 REG LCFF_X22_Y6_N25 5 " "Info: 12: + IC(0.827 ns) + CELL(0.666 ns) = 16.618 ns; Loc. = LCFF_X22_Y6_N25; Fanout = 5; REG Node = 'hour1\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.493 ns" { cta~69clkctrl hour1[3] } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.502 ns ( 39.13 % ) " "Info: Total cell delay = 6.502 ns ( 39.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.116 ns ( 60.87 % ) " "Info: Total interconnect delay = 10.116 ns ( 60.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.618 ns" { clk clk~clkctrl sound[0] clk_1Hz clk_1Hz~clkctrl minclk ct1~69 ct1~69clkctrl hclk cta~69 cta~69clkctrl hour1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "16.618 ns" { clk clk~combout clk~clkctrl sound[0] clk_1Hz clk_1Hz~clkctrl minclk ct1~69 ct1~69clkctrl hclk cta~69 cta~69clkctrl hour1[3] } { 0.000ns 0.000ns 0.143ns 0.829ns 0.394ns 0.757ns 0.834ns 0.638ns 2.385ns 0.840ns 1.477ns 0.992ns 0.827ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.970ns 0.000ns 0.970ns 0.206ns 0.000ns 0.970ns 0.650ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.920 ns" { clk clk~clkctrl num4[0] cta~69 cta~69clkctrl hour1[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.920 ns" { clk clk~combout clk~clkctrl num4[0] cta~69 cta~69clkctrl hour1[5] } { 0.000ns 0.000ns 0.143ns 0.829ns 0.000ns 0.992ns 0.827ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.393ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.618 ns" { clk clk~clkctrl sound[0] clk_1Hz clk_1Hz~clkctrl minclk ct1~69 ct1~69clkctrl hclk cta~69 cta~69clkctrl hour1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "16.618 ns" { clk clk~combout clk~clkctrl sound[0] clk_1Hz clk_1Hz~clkctrl minclk ct1~69 ct1~69clkctrl hclk cta~69 cta~69clkctrl hour1[3] } { 0.000ns 0.000ns 0.143ns 0.829ns 0.394ns 0.757ns 0.834ns 0.638ns 2.385ns 0.840ns 1.477ns 0.992ns 0.827ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.970ns 0.000ns 0.970ns 0.206ns 0.000ns 0.970ns 0.650ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 131 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 131 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.636 ns" { hour1[3] Equal9~96 Add10~49 Add10~50 hour1~196 hour1[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.636 ns" { hour1[3] Equal9~96 Add10~49 Add10~50 hour1~196 hour1[5] } { 0.000ns 0.483ns 0.409ns 0.000ns 0.379ns 0.000ns } { 0.000ns 0.646ns 0.735ns 0.506ns 0.370ns 0.108ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.920 ns" { clk clk~clkctrl num4[0] cta~69 cta~69clkctrl hour1[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.920 ns" { clk clk~combout clk~clkctrl num4[0] cta~69 cta~69clkctrl hour1[5] } { 0.000ns 0.000ns 0.143ns 0.829ns 0.000ns 0.992ns 0.827ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.393ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.618 ns" { clk clk~clkctrl sound[0] clk_1Hz clk_1Hz~clkctrl minclk ct1~69 ct1~69clkctrl hclk cta~69 cta~69clkctrl hour1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "16.618 ns" { clk clk~combout clk~clkctrl sound[0] clk_1Hz clk_1Hz~clkctrl minclk ct1~69 ct1~69clkctrl hclk cta~69 cta~69clkctrl hour1[3] } { 0.000ns 0.000ns 0.143ns 0.829ns 0.394ns 0.757ns 0.834ns 0.638ns 2.385ns 0.840ns 1.477ns 0.992ns 0.827ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.970ns 0.000ns 0.970ns 0.206ns 0.000ns 0.970ns 0.650ns 0.000ns 0.666ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "mode register register m\[0\] m\[1\] 340.02 MHz Internal " "Info: Clock \"mode\" Internal fmax is restricted to 340.02 MHz between source register \"m\[0\]\" and destination register \"m\[1\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.778 ns + Longest register register " "Info: + Longest register to register delay is 0.778 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns m\[0\] 1 REG LCFF_X21_Y6_N19 26 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y6_N19; Fanout = 26; REG Node = 'm\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { m[0] } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.464 ns) + CELL(0.206 ns) 0.670 ns m~41 2 COMB LCCOMB_X21_Y6_N2 1 " "Info: 2: + IC(0.464 ns) + CELL(0.206 ns) = 0.670 ns; Loc. = LCCOMB_X21_Y6_N2; Fanout = 1; COMB Node = 'm~41'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.670 ns" { m[0] m~41 } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.778 ns m\[1\] 3 REG LCFF_X21_Y6_N3 26 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.778 ns; Loc. = LCFF_X21_Y6_N3; Fanout = 26; REG Node = 'm\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { m~41 m[1] } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.314 ns ( 40.36 % ) " "Info: Total cell delay = 0.314 ns ( 40.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.464 ns ( 59.64 % ) " "Info: Total interconnect delay = 0.464 ns ( 59.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.778 ns" { m[0] m~41 m[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.778 ns" { m[0] m~41 m[1] } { 0.000ns 0.464ns 0.000ns } { 0.000ns 0.206ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mode destination 2.721 ns + Shortest register " "Info: + Shortest clock path from clock \"mode\" to destination register is 2.721 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns mode 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'mode'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { mode } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.233 ns mode~clkctrl 2 COMB CLKCTRL_G1 2 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G1; Fanout = 2; COMB Node = 'mode~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.143 ns" { mode mode~clkctrl } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.822 ns) + CELL(0.666 ns) 2.721 ns m\[1\] 3 REG LCFF_X21_Y6_N3 26 " "Info: 3: + IC(0.822 ns) + CELL(0.666 ns) = 2.721 ns; Loc. = LCFF_X21_Y6_N3; Fanout = 26; REG Node = 'm\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.488 ns" { mode~clkctrl m[1] } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 64.54 % ) " "Info: Total cell delay = 1.756 ns ( 64.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.965 ns ( 35.46 % ) " "Info: Total interconnect delay = 0.965 ns ( 35.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.721 ns" { mode mode~clkctrl m[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.721 ns" { mode mode~combout mode~clkctrl m[1] } { 0.000ns 0.000ns 0.143ns 0.822ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mode source 2.721 ns - Longest register " "Info: - Longest clock path from clock \"mode\" to source register is 2.721 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns mode 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'mode'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { mode } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.233 ns mode~clkctrl 2 COMB CLKCTRL_G1 2 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.233 ns; Loc. = CLKCTRL_G1; Fanout = 2; COMB Node = 'mode~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.143 ns" { mode mode~clkctrl } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.822 ns) + CELL(0.666 ns) 2.721 ns m\[0\] 3 REG LCFF_X21_Y6_N19 26 " "Info: 3: + IC(0.822 ns) + CELL(0.666 ns) = 2.721 ns; Loc. = LCFF_X21_Y6_N19; Fanout = 26; REG Node = 'm\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.488 ns" { mode~clkctrl m[0] } "NODE_NAME" } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 64.54 % ) " "Info: Total cell delay = 1.756 ns ( 64.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.965 ns ( 35.46 % ) " "Info: Total interconnect delay = 0.965 ns ( 35.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.721 ns" { mode mode~clkctrl m[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.721 ns" { mode mode~combout mode~clkctrl m[0] } { 0.000ns 0.000ns 0.143ns 0.822ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.721 ns" { mode mode~clkctrl m[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.721 ns" { mode mode~combout mode~clkctrl m[1] } { 0.000ns 0.000ns 0.143ns 0.822ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.721 ns" { mode mode~clkctrl m[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.721 ns" { mode mode~combout mode~clkctrl m[0] } { 0.000ns 0.000ns 0.143ns 0.822ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.778 ns" { m[0] m~41 m[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.778 ns" { m[0] m~41 m[1] } { 0.000ns 0.464ns 0.000ns } { 0.000ns 0.206ns 0.108ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.721 ns" { mode mode~clkctrl m[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.721 ns" { mode mode~combout mode~clkctrl m[1] } { 0.000ns 0.000ns 0.143ns 0.822ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.721 ns" { mode mode~clkctrl m[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.721 ns" { mode mode~combout mode~clkctrl m[0] } { 0.000ns 0.000ns 0.143ns 0.822ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { m[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { m[1] } {  } {  } } } { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}