clock.tan.qmsg

一些Verilog学习程序A

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 22 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "mode " "Info: Assuming node \"mode\" is an undefined clock" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 22 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "mode" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "turn " "Info: Assuming node \"turn\" is an undefined clock" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 22 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "turn" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "20 " "Warning: Found 20 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "counta " "Info: Detected ripple clock \"counta\" as buffer" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 31 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "counta" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "countb " "Info: Detected ripple clock \"countb\" as buffer" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 31 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "countb" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count2 " "Info: Detected ripple clock \"count2\" as buffer" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 31 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count1 " "Info: Detected ripple clock \"count1\" as buffer" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 31 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Decoder0~28 " "Info: Detected gated clock \"Decoder0~28\" as buffer" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Decoder0~28" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "num4\[0\] " "Info: Detected ripple clock \"num4\[0\]\" as buffer" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 95 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "num4\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "hclk " "Info: Detected ripple clock \"hclk\" as buffer" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 29 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "hclk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "cta~69 " "Info: Detected gated clock \"cta~69\" as buffer" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cta~69" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "num2\[0\] " "Info: Detected ripple clock \"num2\[0\]\" as buffer" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 79 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "num2\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "ctb~10 " "Info: Detected gated clock \"ctb~10\" as buffer" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ctb~10" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "num1\[0\] " "Info: Detected ripple clock \"num1\[0\]\" as buffer" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 70 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "num1\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "ct2~10 " "Info: Detected gated clock \"ct2~10\" as buffer" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ct2~10" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fm\[1\] " "Info: Detected ripple clock \"fm\[1\]\" as buffer" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 46 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fm\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "minclk " "Info: Detected ripple clock \"minclk\" as buffer" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 29 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "minclk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "num3\[0\] " "Info: Detected ripple clock \"num3\[0\]\" as buffer" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 87 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "num3\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "ct1~69 " "Info: Detected gated clock \"ct1~69\" as buffer" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ct1~69" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "m\[0\] " "Info: Detected ripple clock \"m\[0\]\" as buffer" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "m\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "m\[1\] " "Info: Detected ripple clock \"m\[1\]\" as buffer" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 44 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "m\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "sound\[0\] " "Info: Detected ripple clock \"sound\[0\]\" as buffer" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 39 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sound\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk_1Hz " "Info: Detected ripple clock \"clk_1Hz\" as buffer" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 29 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk_1Hz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}