clock.tan.qmsg

一些Verilog学习程序A

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off clock -c clock --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clock -c clock --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "count1 " "Warning: Node \"count1\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 31 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "count2 " "Warning: Node \"count2\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 31 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "countb " "Warning: Node \"countb\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 31 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "counta " "Warning: Node \"counta\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 31 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "hour\[0\]\$latch " "Warning: Node \"hour\[0\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "hour\[1\]\$latch " "Warning: Node \"hour\[1\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "hour\[2\]\$latch " "Warning: Node \"hour\[2\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "hour\[3\]\$latch " "Warning: Node \"hour\[3\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "hour\[4\]\$latch " "Warning: Node \"hour\[4\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "hour\[5\]\$latch " "Warning: Node \"hour\[5\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "hour\[6\]\$latch " "Warning: Node \"hour\[6\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "hour\[7\]\$latch " "Warning: Node \"hour\[7\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "min\[0\]\$latch " "Warning: Node \"min\[0\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "min\[1\]\$latch " "Warning: Node \"min\[1\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "min\[2\]\$latch " "Warning: Node \"min\[2\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "min\[3\]\$latch " "Warning: Node \"min\[3\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "min\[4\]\$latch " "Warning: Node \"min\[4\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "min\[5\]\$latch " "Warning: Node \"min\[5\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "min\[6\]\$latch " "Warning: Node \"min\[6\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "min\[7\]\$latch " "Warning: Node \"min\[7\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sec\[0\]\$latch " "Warning: Node \"sec\[0\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "always15_433 " "Warning: Node \"always15_433\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sec\[1\]\$latch " "Warning: Node \"sec\[1\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sec\[2\]\$latch " "Warning: Node \"sec\[2\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sec\[3\]\$latch " "Warning: Node \"sec\[3\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sec\[4\]\$latch " "Warning: Node \"sec\[4\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sec\[5\]\$latch " "Warning: Node \"sec\[5\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sec\[6\]\$latch " "Warning: Node \"sec\[6\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sec\[7\]\$latch " "Warning: Node \"sec\[7\]\$latch\" is a latch" {  } { { "clock.v" "" { Text "F:/Verilog/多功能数字钟/clock.v" 152 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}