clock.map.summary

来自「一些Verilog学习程序A」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Sat Aug 15 23:11:09 2009
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : clock
Top-level Entity Name : clock
Family : Cyclone II
Total logic elements : 172
Total registers : 61
Total pins : 33
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0