📄 clock.map.rpt
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; min[1]$latch ; Decoder0 ; yes ;
; min[2]$latch ; Decoder0 ; yes ;
; min[3]$latch ; Decoder0 ; yes ;
; min[4]$latch ; Decoder0 ; yes ;
; min[5]$latch ; Decoder0 ; yes ;
; min[6]$latch ; Decoder0 ; yes ;
; min[7]$latch ; Decoder0 ; yes ;
; count2 ; fm[1] ; yes ;
; countb ; fm[1] ; yes ;
; counta ; fm[1] ; yes ;
; count1 ; fm[1] ; yes ;
; sec[0]$latch ; Decoder0 ; yes ;
; always15_433 ; Decoder0 ; yes ;
; sec[1]$latch ; Decoder0 ; yes ;
; sec[2]$latch ; Decoder0 ; yes ;
; sec[3]$latch ; Decoder0 ; yes ;
; sec[4]$latch ; Decoder0 ; yes ;
; sec[5]$latch ; Decoder0 ; yes ;
; sec[6]$latch ; Decoder0 ; yes ;
; sec[7]$latch ; Decoder0 ; yes ;
; Number of user-specified and inferred latches = 29 ; ; ;
+-----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 61 ;
; Number of registers using Synchronous Clear ; 4 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |clock|sec1[1] ;
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |clock|amin[3] ;
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |clock|ahour[3] ;
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |clock|min1[0] ;
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |clock|hour1[1] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Sat Aug 15 23:11:05 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock
Info: Found 1 design units, including 1 entities, in source file clock.v
Info: Found entity 1: clock
Info: Elaborating entity "clock" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at clock.v(38): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at clock.v(44): truncated value with size 32 to match size of target (2)
Info (10264): Verilog HDL Case Statement information at clock.v(49): all case item expressions in this case statement are onehot
Warning (10240): Verilog HDL Always Construct warning at clock.v(67): inferring latch(es) for variable "count1", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at clock.v(50): inferred latch for "count1"
Warning (10240): Verilog HDL Always Construct warning at clock.v(67): inferring latch(es) for variable "counta", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at clock.v(50): inferred latch for "counta"
Warning (10240): Verilog HDL Always Construct warning at clock.v(67): inferring latch(es) for variable "count2", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at clock.v(57): inferred latch for "count2"
Warning (10240): Verilog HDL Always Construct warning at clock.v(67): inferring latch(es) for variable "countb", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at clock.v(57): inferred latch for "countb"
Warning (10230): Verilog HDL assignment warning at clock.v(73): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at clock.v(82): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at clock.v(90): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at clock.v(98): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at clock.v(101): truncated value with size 2 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at clock.v(102): truncated value with size 2 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at clock.v(103): truncated value with size 2 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at clock.v(104): truncated value with size 2 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at clock.v(113): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at clock.v(114): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at clock.v(124): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at clock.v(125): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at clock.v(133): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at clock.v(134): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at clock.v(138): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at clock.v(139): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at clock.v(143): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at clock.v(144): truncated value with size 32 to match size of target (4)
Warning (10270): Verilog HDL statement warning at clock.v(152): incomplete Case Statement has no default case item
Warning (10240): Verilog HDL Always Construct warning at clock.v(152): inferring latch(es) for variable "hour", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "hour[7]"
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "hour[6]"
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "hour[5]"
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "hour[4]"
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "hour[3]"
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "hour[2]"
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "hour[1]"
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "hour[0]"
Warning (10240): Verilog HDL Always Construct warning at clock.v(152): inferring latch(es) for variable "min", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "min[7]"
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "min[6]"
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "min[5]"
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "min[4]"
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "min[3]"
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "min[2]"
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "min[1]"
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "min[0]"
Warning (10240): Verilog HDL Always Construct warning at clock.v(152): inferring latch(es) for variable "sec", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "sec[7]"
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "sec[6]"
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "sec[5]"
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "sec[4]"
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "sec[3]"
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "sec[2]"
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "sec[1]"
Info (10041): Verilog HDL or VHDL info at clock.v(152): inferred latch for "sec[0]"
Warning (10230): Verilog HDL assignment warning at clock.v(161): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at clock.v(162): truncated value with size 32 to match size of target (1)
Warning: Reduced register "num1[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "num2[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "num3[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "num4[1]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
Info: Duplicate register "fm[0]" merged to single register "fm[1]"
Info: Duplicate registers merged to single register
Info: Duplicate register "clk_2Hz" merged to single register "sound[0]"
Warning: Latch hour[0]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch hour[1]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch hour[2]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch hour[3]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch hour[4]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch hour[5]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch hour[6]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch hour[7]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch min[0]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch min[1]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch min[2]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch min[3]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch min[4]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch min[5]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch min[6]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch min[7]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch always15_433 has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Info: Implemented 206 device resources after synthesis - the final resource count might be different
Info: Implemented 5 input pins
Info: Implemented 28 output pins
Info: Implemented 173 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 68 warnings
Info: Processing ended: Sat Aug 15 23:11:09 2009
Info: Elapsed time: 00:00:05
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