📄 seg71.fit.rpt
字号:
; 7 ; 0 ;
; 8 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 3.50) ; Number of LABs (Total = 4) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 3 ;
; 4 ; 0 ;
; 5 ; 1 ;
+---------------------------------------------+-----------------------------+
+--------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+---------------------+
; Option ; Setting ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As input tri-stated ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+---------------------+
+----------------------------+
; Advanced Data - General ;
+--------------------+-------+
; Name ; Value ;
+--------------------+-------+
; Desired User Slack ; 0 ;
; Fit Attempts ; 1 ;
+--------------------+-------+
+------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation ;
+--------------------------------------------------------------------------------+---------+
; Name ; Value ;
+--------------------------------------------------------------------------------+---------+
; Mid Wire Use - Fit Attempt 1 ; 5 ;
; Mid Slack - Fit Attempt 1 ; -9266 ;
; Internal Atom Count - Fit Attempt 1 ; 30 ;
; LE/ALM Count - Fit Attempt 1 ; 30 ;
; LAB Count - Fit Attempt 1 ; 4 ;
; Outputs per Lab - Fit Attempt 1 ; 4.250 ;
; Inputs per LAB - Fit Attempt 1 ; 1.500 ;
; Global Inputs per LAB - Fit Attempt 1 ; 1.000 ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1 ; 0:4 ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1 ; 0:4 ;
; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:4 ;
; LAB Constraint 'un-route combination' - Fit Attempt 1 ; 0:4 ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1 ; 0:2;1:2 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1 ; 0:2;1:2 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1 ; 0:4 ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1 ; 0:4 ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1 ; 0:4 ;
; LAB Constraint 'global control signals' - Fit Attempt 1 ; 0:2;2:2 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:2;1:2 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1 ; 0:4 ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1 ; 0:2;1:2 ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1 ; 0:4 ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1 ; 0:2;1:2 ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:2;1:2 ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:4 ;
; LEs in Chains - Fit Attempt 1 ; 15 ;
; LEs in Long Chains - Fit Attempt 1 ; 15 ;
; LABs with Chains - Fit Attempt 1 ; 2 ;
; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;
; Time - Fit Attempt 1 ; 0 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.015 ;
+--------------------------------------------------------------------------------+---------+
+----------------------------------------------+
; Advanced Data - Placement ;
+-------------------------------------+--------+
; Name ; Value ;
+-------------------------------------+--------+
; Early Wire Use - Fit Attempt 1 ; 1 ;
; Early Slack - Fit Attempt 1 ; -10504 ;
; Mid Wire Use - Fit Attempt 1 ; 2 ;
; Mid Slack - Fit Attempt 1 ; -9867 ;
; Late Wire Use - Fit Attempt 1 ; 2 ;
; Late Slack - Fit Attempt 1 ; -9782 ;
; Time - Fit Attempt 1 ; 1 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.766 ;
+-------------------------------------+--------+
+---------------------------------------------+
; Advanced Data - Routing ;
+-------------------------------------+-------+
; Name ; Value ;
+-------------------------------------+-------+
; Early Slack - Fit Attempt 1 ; -9578 ;
; Mid Slack - Fit Attempt 1 ; -9840 ;
; Late Slack - Fit Attempt 1 ; -9840 ;
; Late Slack - Fit Attempt 1 ; -9840 ;
; Late Wire Use - Fit Attempt 1 ; 2 ;
; Time - Fit Attempt 1 ; 0 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.094 ;
+-------------------------------------+-------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Sun Jan 11 21:51:48 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off seg71 -c seg71
Info: Selected device EPM240T100C5 for design "seg71"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EPM240T100I5 is compatible
Info: Device EPM570T100C5 is compatible
Info: Device EPM570T100I5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 12
Info: Automatically promoted signal "rst" to use Global clock
Info: Pin "rst" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:01
Info: Estimated most critical path is register to pin delay of 6.392 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y4; Fanout = 15; REG Node = 'cnt_scan[15]'
Info: 2: + IC(1.557 ns) + CELL(0.200 ns) = 1.757 ns; Loc. = LAB_X5_Y4; Fanout = 2; COMB Node = 'Decoder1~92'
Info: 3: + IC(2.313 ns) + CELL(2.322 ns) = 6.392 ns; Loc. = PIN_78; Fanout = 0; PIN Node = 'dataout[5]'
Info: Total cell delay = 2.522 ns ( 39.46 % )
Info: Total interconnect delay = 3.870 ns ( 60.54 % )
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
Info: Pin dataout[0] has VCC driving its datain port
Info: Quartus II Fitter was successful. 0 errors, 1 warning
Info: Processing ended: Sun Jan 11 21:51:50 2009
Info: Elapsed time: 00:00:03
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in E:/Verilog/接口实验/7段数码管/seg71/seg71.fit.smsg.
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