serial.fit.rpt

一些Verilog学习程序B

; Name                                                                           ; Value           ;
+--------------------------------------------------------------------------------+-----------------+
; Mid Wire Use - Fit Attempt 1                                                   ; 33              ;
; Mid Slack - Fit Attempt 1                                                      ; -14880          ;
; Internal Atom Count - Fit Attempt 1                                            ; 169             ;
; LE/ALM Count - Fit Attempt 1                                                   ; 169             ;
; LAB Count - Fit Attempt 1                                                      ; 23              ;
; Outputs per Lab - Fit Attempt 1                                                ; 4.913           ;
; Inputs per LAB - Fit Attempt 1                                                 ; 6.696           ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 1.261           ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:23            ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:14;1:8;2:1    ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:10;1:8;2:5    ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:10;1:8;2:5    ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:5;1:9;2:7;3:2 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:5;1:9;2:7;3:2 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:15;1:8        ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:23            ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:14;1:8;2:1    ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:5;1:7;2:11    ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:5;1:17;2:1    ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:23            ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:5;1:18        ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:11;1:12       ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:4;1:19        ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:19;1:4        ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:23            ;
; LEs in Chains - Fit Attempt 1                                                  ; 36              ;
; LEs in Long Chains - Fit Attempt 1                                             ; 36              ;
; LABs with Chains - Fit Attempt 1                                               ; 4               ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0               ;
; Time - Fit Attempt 1                                                           ; 2               ;
; Time in tsm_tan.dll - Fit Attempt 1                                            ; 0.016           ;
+--------------------------------------------------------------------------------+-----------------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Wire Use - Fit Attempt 1      ; 7      ;
; Early Slack - Fit Attempt 1         ; -15764 ;
; Mid Wire Use - Fit Attempt 1        ; 13     ;
; Mid Slack - Fit Attempt 1           ; -14604 ;
; Late Wire Use - Fit Attempt 1       ; 14     ;
; Late Slack - Fit Attempt 1          ; -14604 ;
; Time - Fit Attempt 1                ; 2      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.673  ;
+-------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1         ; -14045 ;
; Early Wire Use - Fit Attempt 1      ; 7      ;
; Peak Regional Wire - Fit Attempt 1  ; 6      ;
; Mid Slack - Fit Attempt 1           ; -15451 ;
; Late Slack - Fit Attempt 1          ; -15451 ;
; Late Slack - Fit Attempt 1          ; -15451 ;
; Late Wire Use - Fit Attempt 1       ; 15     ;
; Time - Fit Attempt 1                ; 1      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.203  ;
+-------------------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon May 25 23:53:20 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off serial -c serial
Info: Selected device EPM240GT100C5 for design "serial"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240GT100I5 is compatible
    Info: Device EPM570GT100C5 is compatible
    Info: Device EPM570GT100I5 is compatible
Info: No exact pin location assignment(s) for 1 pins of 22 total pins
    Info: Pin lowbit not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 12
Info: Automatically promoted some destinations of signal "clkbaud8x" to use Global clock
    Info: Destination "clkbaud8x" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "rst" to use Global clock
    Info: Destination "clkbaud8x" may be non-global or may not use global clock
    Info: Destination "key_entry1" may be non-global or may not use global clock
    Info: Destination "div_reg[10]~328" may be non-global or may not use global clock
    Info: Destination "cnt_delay[11]~1017" may be non-global or may not use global clock
    Info: Destination "start_delaycnt" may be non-global or may not use global clock
    Info: Destination "cnt_delay[11]~1018" may be non-global or may not use global clock
Info: Pin "rst" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 5 total pin(s) used --  33 pins available
        Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 16 total pin(s) used --  26 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:02
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:02
Info: Estimated most critical path is register to pin delay of 7.563 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X5_Y4; Fanout = 9; REG Node = 'rxd_buf[3]'
    Info: 2: + IC(1.232 ns) + CELL(0.200 ns) = 1.432 ns; Loc. = LAB_X5_Y4; Fanout = 1; COMB Node = 'WideOr9~612'
    Info: 3: + IC(0.917 ns) + CELL(0.740 ns) = 3.089 ns; Loc. = LAB_X6_Y4; Fanout = 1; COMB Node = 'WideOr9~613'
    Info: 4: + IC(0.667 ns) + CELL(0.914 ns) = 4.670 ns; Loc. = LAB_X7_Y4; Fanout = 1; COMB Node = 'WideOr9~615'
    Info: 5: + IC(0.571 ns) + CELL(2.322 ns) = 7.563 ns; Loc. = PIN_76; Fanout = 0; PIN Node = 'seg_data[6]'
    Info: Total cell delay = 4.176 ns ( 55.22 % )
    Info: Total interconnect delay = 3.387 ns ( 44.78 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 5% of the available device resources. Peak interconnect usage is 5%
    Info: The peak interconnect region extends from location x0_y0 to location x8_y5
Info: Fitter routing operations ending: elapsed time is 00:00:01
Warning: Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin en[0] has GND driving its datain port
    Info: Pin en[1] has GND driving its datain port
    Info: Pin en[2] has GND driving its datain port
    Info: Pin en[3] has GND driving its datain port
    Info: Pin en[4] has GND driving its datain port
    Info: Pin en[5] has GND driving its datain port
    Info: Pin en[6] has GND driving its datain port
    Info: Pin en[7] has GND driving its datain port
    Info: Pin lowbit has GND driving its datain port
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Processing ended: Mon May 25 23:53:26 2009
    Info: Elapsed time: 00:00:06


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in E:/EPM240学习板B/Verilog/接口实验/串口/serial.fit.smsg.