bcd.tan.rpt

一些Verilog学习程序B

; N/A   ; None              ; 10.183 ns       ; a[1] ; c[4] ;
; N/A   ; None              ; 10.180 ns       ; a[1] ; c[3] ;
; N/A   ; None              ; 10.061 ns       ; a[0] ; c[5] ;
; N/A   ; None              ; 9.988 ns        ; a[2] ; c[1] ;
; N/A   ; None              ; 9.987 ns        ; a[2] ; c[2] ;
; N/A   ; None              ; 9.980 ns        ; a[2] ; c[3] ;
; N/A   ; None              ; 9.978 ns        ; a[2] ; c[4] ;
; N/A   ; None              ; 9.814 ns        ; a[3] ; c[1] ;
; N/A   ; None              ; 9.813 ns        ; a[3] ; c[2] ;
; N/A   ; None              ; 9.806 ns        ; a[3] ; c[3] ;
; N/A   ; None              ; 9.804 ns        ; a[3] ; c[4] ;
; N/A   ; None              ; 9.450 ns        ; a[0] ; c[2] ;
; N/A   ; None              ; 9.450 ns        ; a[0] ; c[1] ;
; N/A   ; None              ; 9.449 ns        ; a[0] ; c[4] ;
; N/A   ; None              ; 9.446 ns        ; a[0] ; c[3] ;
+-------+-------------------+-----------------+------+------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Jan 11 21:24:30 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off bcd -c bcd
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 119.85 MHz between source register "cnt[17]" and destination register "en[0]~reg0" (period= 8.344 ns)
    Info: + Longest register to register delay is 7.635 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y2_N5; Fanout = 4; REG Node = 'cnt[17]'
        Info: 2: + IC(1.373 ns) + CELL(0.511 ns) = 1.884 ns; Loc. = LC_X6_Y2_N7; Fanout = 1; COMB Node = 'Equal0~191'
        Info: 3: + IC(0.726 ns) + CELL(0.740 ns) = 3.350 ns; Loc. = LC_X6_Y2_N6; Fanout = 1; COMB Node = 'Equal0~193'
        Info: 4: + IC(0.779 ns) + CELL(0.511 ns) = 4.640 ns; Loc. = LC_X6_Y2_N4; Fanout = 4; COMB Node = 'Equal0~197'
        Info: 5: + IC(1.752 ns) + CELL(1.243 ns) = 7.635 ns; Loc. = LC_X5_Y4_N4; Fanout = 4; REG Node = 'en[0]~reg0'
        Info: Total cell delay = 3.005 ns ( 39.36 % )
        Info: Total interconnect delay = 4.630 ns ( 60.64 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 22; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y4_N4; Fanout = 4; REG Node = 'en[0]~reg0'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
        Info: - Longest clock path from clock "clk" to source register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 22; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y2_N5; Fanout = 4; REG Node = 'cnt[17]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "c[7]" through register "en[1]~reg0" is 12.905 ns
    Info: + Longest clock path from clock "clk" to source register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 22; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y4_N0; Fanout = 4; REG Node = 'en[1]~reg0'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 9.181 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y4_N0; Fanout = 4; REG Node = 'en[1]~reg0'
        Info: 2: + IC(0.997 ns) + CELL(0.511 ns) = 1.508 ns; Loc. = LC_X5_Y4_N6; Fanout = 4; COMB Node = 'Selector0~24'
        Info: 3: + IC(1.157 ns) + CELL(0.200 ns) = 2.865 ns; Loc. = LC_X5_Y4_N9; Fanout = 7; COMB Node = 'Selector0~25'
        Info: 4: + IC(1.265 ns) + CELL(0.914 ns) = 5.044 ns; Loc. = LC_X6_Y4_N6; Fanout = 1; COMB Node = 'WideOr3~15'
        Info: 5: + IC(1.815 ns) + CELL(2.322 ns) = 9.181 ns; Loc. = PIN_76; Fanout = 0; PIN Node = 'c[7]'
        Info: Total cell delay = 3.947 ns ( 42.99 % )
        Info: Total interconnect delay = 5.234 ns ( 57.01 % )
Info: Longest tpd from source pin "a[1]" to destination pin "c[7]" is 11.399 ns
    Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_28; Fanout = 4; PIN Node = 'a[1]'
    Info: 2: + IC(2.814 ns) + CELL(0.511 ns) = 4.457 ns; Loc. = LC_X5_Y4_N2; Fanout = 1; COMB Node = 'Selector3~100'
    Info: 3: + IC(0.728 ns) + CELL(0.200 ns) = 5.385 ns; Loc. = LC_X5_Y4_N1; Fanout = 7; COMB Node = 'Selector3~101'
    Info: 4: + IC(1.366 ns) + CELL(0.511 ns) = 7.262 ns; Loc. = LC_X6_Y4_N6; Fanout = 1; COMB Node = 'WideOr3~15'
    Info: 5: + IC(1.815 ns) + CELL(2.322 ns) = 11.399 ns; Loc. = PIN_76; Fanout = 0; PIN Node = 'c[7]'
    Info: Total cell delay = 4.676 ns ( 41.02 % )
    Info: Total interconnect delay = 6.723 ns ( 58.98 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Jan 11 21:24:31 2009
    Info: Elapsed time: 00:00:02