div.fit.rpt

一些Verilog学习程序B

+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                    ;
+--------------------------------------------------------------------------------+---------+
; Name                                                                           ; Value   ;
+--------------------------------------------------------------------------------+---------+
; Mid Wire Use - Fit Attempt 1                                                   ; 5       ;
; Mid Slack - Fit Attempt 1                                                      ; -12083  ;
; Internal Atom Count - Fit Attempt 1                                            ; 21      ;
; LE/ALM Count - Fit Attempt 1                                                   ; 21      ;
; LAB Count - Fit Attempt 1                                                      ; 3       ;
; Outputs per Lab - Fit Attempt 1                                                ; 3.333   ;
; Inputs per LAB - Fit Attempt 1                                                 ; 6.000   ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 0.000   ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:3     ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:3     ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:3     ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:3     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:3     ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:3     ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:3     ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:3     ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:3     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:3     ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:3     ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:3     ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:3     ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:3     ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:1;1:2 ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:3     ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:3     ;
; LEs in Chains - Fit Attempt 1                                                  ; 0       ;
; LEs in Long Chains - Fit Attempt 1                                             ; 0       ;
; LABs with Chains - Fit Attempt 1                                               ; 0       ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0       ;
; Time - Fit Attempt 1                                                           ; 0       ;
; Time in tsm_tan.dll - Fit Attempt 1                                            ; 0.015   ;
+--------------------------------------------------------------------------------+---------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Wire Use - Fit Attempt 1      ; 1      ;
; Early Slack - Fit Attempt 1         ; -11391 ;
; Mid Wire Use - Fit Attempt 1        ; 3      ;
; Mid Slack - Fit Attempt 1           ; -11370 ;
; Late Wire Use - Fit Attempt 1       ; 3      ;
; Late Slack - Fit Attempt 1          ; -11370 ;
; Time - Fit Attempt 1                ; 1      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.313  ;
+-------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1         ; -9769  ;
; Early Wire Use - Fit Attempt 1      ; 2      ;
; Peak Regional Wire - Fit Attempt 1  ; 2      ;
; Mid Slack - Fit Attempt 1           ; -11226 ;
; Late Slack - Fit Attempt 1          ; -10931 ;
; Late Slack - Fit Attempt 1          ; -10931 ;
; Late Wire Use - Fit Attempt 1       ; 3      ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016  ;
+-------------------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Jan 11 21:12:57 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off div -c div
Info: Selected device EPM240T100C5 for design "div"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Info: No exact pin location assignment(s) for 7 pins of 22 total pins
    Info: Pin en[1] not assigned to an exact location on the device
    Info: Pin en[2] not assigned to an exact location on the device
    Info: Pin en[3] not assigned to an exact location on the device
    Info: Pin en[4] not assigned to an exact location on the device
    Info: Pin en[5] not assigned to an exact location on the device
    Info: Pin en[6] not assigned to an exact location on the device
    Info: Pin en[7] not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 7 (unused VREF, 3.30 VCCIO, 0 input, 7 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 6 total pin(s) used --  32 pins available
        Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 9 total pin(s) used --  33 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:01
Info: Estimated most critical path is pin to pin delay of 11.870 ns
    Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_28; Fanout = 9; PIN Node = 'a[1]'
    Info: 2: + IC(2.291 ns) + CELL(0.200 ns) = 3.623 ns; Loc. = LAB_X3_Y1; Fanout = 1; COMB Node = 'LessThan2~415'
    Info: 3: + IC(0.440 ns) + CELL(0.740 ns) = 4.803 ns; Loc. = LAB_X3_Y1; Fanout = 1; COMB Node = 'LessThan2~416'
    Info: 4: + IC(0.266 ns) + CELL(0.914 ns) = 5.983 ns; Loc. = LAB_X3_Y1; Fanout = 4; COMB Node = 'LessThan2~419'
    Info: 5: + IC(0.980 ns) + CELL(0.200 ns) = 7.163 ns; Loc. = LAB_X3_Y1; Fanout = 1; COMB Node = 'WideOr0~145'
    Info: 6: + IC(2.385 ns) + CELL(2.322 ns) = 11.870 ns; Loc. = PIN_76; Fanout = 0; PIN Node = 'c[7]'
    Info: Total cell delay = 5.508 ns ( 46.40 % )
    Info: Total interconnect delay = 6.362 ns ( 53.60 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 2% of the available device resources. Peak interconnect usage is 2%
    Info: The peak interconnect region extends from location x0_y0 to location x8_y5
Info: Fitter routing operations ending: elapsed time is 00:00:00
Warning: Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin c[0] has VCC driving its datain port
    Info: Pin en[0] has GND driving its datain port
    Info: Pin en[1] has GND driving its datain port
    Info: Pin en[2] has GND driving its datain port
    Info: Pin en[3] has GND driving its datain port
    Info: Pin en[4] has GND driving its datain port
    Info: Pin en[5] has GND driving its datain port
    Info: Pin en[6] has GND driving its datain port
    Info: Pin en[7] has GND driving its datain port
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Jan 11 21:13:02 2009
    Info: Elapsed time: 00:00:06


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in E:/Verilog/基础实验/除法器/div.fit.smsg.